@@ -470,6 +470,28 @@ define <vscale x 2 x i64> @select_nxv2i64(<vscale x 2 x i1> %a, <vscale x 2 x i6
470470 ret <vscale x 2 x i64 > %v
471471}
472472
473+ define <vscale x 2 x i64 > @select_nxv2i64_constant_true (<vscale x 2 x i1 > %a , <vscale x 2 x i64 > %b , i32 zeroext %evl ) {
474+ ; CHECK-LABEL: select_nxv2i64_constant_true:
475+ ; CHECK: # %bb.0:
476+ ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
477+ ; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
478+ ; CHECK-NEXT: ret
479+ %v = call <vscale x 2 x i64 > @llvm.vp.select.nxv2i64 (<vscale x 2 x i1 > %a , <vscale x 2 x i64 > splat (i64 -1 ), <vscale x 2 x i64 > %b , i32 %evl )
480+ ret <vscale x 2 x i64 > %v
481+ }
482+
483+ define <vscale x 2 x i64 > @select_nxv2i64_constant_false (<vscale x 2 x i1 > %a , <vscale x 2 x i64 > %b , i32 zeroext %evl ) {
484+ ; CHECK-LABEL: select_nxv2i64_constant_false:
485+ ; CHECK: # %bb.0:
486+ ; CHECK-NEXT: li a1, 100
487+ ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
488+ ; CHECK-NEXT: vmv.v.x v10, a1
489+ ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
490+ ; CHECK-NEXT: ret
491+ %v = call <vscale x 2 x i64 > @llvm.vp.select.nxv2i64 (<vscale x 2 x i1 > %a , <vscale x 2 x i64 > %b , <vscale x 2 x i64 > splat (i64 100 ), i32 %evl )
492+ ret <vscale x 2 x i64 > %v
493+ }
494+
473495declare <vscale x 4 x i64 > @llvm.vp.select.nxv4i64 (<vscale x 4 x i1 >, <vscale x 4 x i64 >, <vscale x 4 x i64 >, i32 )
474496
475497define <vscale x 4 x i64 > @select_nxv4i64 (<vscale x 4 x i1 > %a , <vscale x 4 x i64 > %b , <vscale x 4 x i64 > %c , i32 zeroext %evl ) {
@@ -702,10 +724,10 @@ define <vscale x 16 x double> @select_nxv16f64(<vscale x 16 x i1> %a, <vscale x
702724; CHECK-NEXT: and a4, a5, a4
703725; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
704726; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
705- ; CHECK-NEXT: bltu a2, a1, .LBB48_2
727+ ; CHECK-NEXT: bltu a2, a1, .LBB50_2
706728; CHECK-NEXT: # %bb.1:
707729; CHECK-NEXT: mv a2, a1
708- ; CHECK-NEXT: .LBB48_2 :
730+ ; CHECK-NEXT: .LBB50_2 :
709731; CHECK-NEXT: vmv1r.v v0, v7
710732; CHECK-NEXT: addi a0, sp, 16
711733; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
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