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[GlobalISel] Support saturated truncate
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6 files changed

+292
-1
lines changed

6 files changed

+292
-1
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‎llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -727,6 +727,25 @@ class CombinerHelper {
727727
bool matchUMulHToLShr(MachineInstr &MI) const;
728728
void applyUMulHToLShr(MachineInstr &MI) const;
729729

730+
// Combine trunc(smin(smax(x, C1), C2)) -> truncssat_s(x)
731+
// or trunc(smax(smin(x, C2), C1)) -> truncssat_s(x).
732+
bool matchTruncSSatS(MachineInstr &MI, Register &MatchInfo) const;
733+
void applyTruncSSatS(MachineInstr &MI, Register &MatchInfo) const;
734+
735+
// Combine trunc(smin(smax(x, 0), C)) -> truncssat_u(x)
736+
// or trunc(smax(smin(x, C), 0)) -> truncssat_u(x)
737+
// or trunc(umin(smax(x, 0), C)) -> truncssat_u(x)
738+
bool matchTruncSSatU(MachineInstr &MI, Register &MatchInfo) const;
739+
void applyTruncSSatU(MachineInstr &MI, Register &MatchInfo) const;
740+
741+
// Combine trunc(umin(x, C)) -> truncusat_u(x).
742+
bool matchTruncUSatU(MachineInstr &MI, Register &MatchInfo) const;
743+
void applyTruncUSatU(MachineInstr &MI, Register &MatchInfo) const;
744+
745+
// Combine truncusat_u(fptoui(x)) -> fptoui_sat(x)
746+
bool matchTruncUSatUToFPTOUISat(MachineInstr &MI, Register &MatchInfo) const;
747+
void applyTruncUSatUToFPTOUISat(MachineInstr &MI, Register &MatchInfo) const;
748+
730749
/// Try to transform \p MI by using all of the above
731750
/// combine functions. Returns true if changed.
732751
bool tryCombine(MachineInstr &MI) const;

‎llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -874,6 +874,9 @@ class GCastOp : public GenericMachineInstr {
874874
case TargetOpcode::G_SEXT:
875875
case TargetOpcode::G_SITOFP:
876876
case TargetOpcode::G_TRUNC:
877+
case TargetOpcode::G_TRUNC_SSAT_S:
878+
case TargetOpcode::G_TRUNC_SSAT_U:
879+
case TargetOpcode::G_TRUNC_USAT_U:
877880
case TargetOpcode::G_UITOFP:
878881
case TargetOpcode::G_ZEXT:
879882
case TargetOpcode::G_ANYEXT:
@@ -916,6 +919,30 @@ class GTrunc : public GCastOp {
916919
};
917920
};
918921

922+
/// Represents a saturated trunc from a signed input to a signed result.
923+
class GTruncSSatS : public GCastOp {
924+
public:
925+
static bool classof(const MachineInstr *MI) {
926+
return MI->getOpcode() == TargetOpcode::G_TRUNC_SSAT_S;
927+
};
928+
};
929+
930+
/// Represents a saturated trunc from a signed input to an unsigned result.
931+
class GTruncSSatU : public GCastOp {
932+
public:
933+
static bool classof(const MachineInstr *MI) {
934+
return MI->getOpcode() == TargetOpcode::G_TRUNC_SSAT_U;
935+
};
936+
};
937+
938+
/// Represents a saturated trunc from an unsigned input to an unsigned result.
939+
class GTruncUSatU : public GCastOp {
940+
public:
941+
static bool classof(const MachineInstr *MI) {
942+
return MI->getOpcode() == TargetOpcode::G_TRUNC_USAT_U;
943+
};
944+
};
945+
919946
/// Represents a vscale.
920947
class GVScale : public GenericMachineInstr {
921948
public:

‎llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -740,6 +740,18 @@ m_GFPTrunc(const SrcTy &Src) {
740740
return UnaryOp_match<SrcTy, TargetOpcode::G_FPTRUNC>(Src);
741741
}
742742

743+
template <typename SrcTy>
744+
inline UnaryOp_match<SrcTy, TargetOpcode::G_FPTOSI>
745+
m_GFPToSI(const SrcTy &Src) {
746+
return UnaryOp_match<SrcTy, TargetOpcode::G_FPTOSI>(Src);
747+
}
748+
749+
template <typename SrcTy>
750+
inline UnaryOp_match<SrcTy, TargetOpcode::G_FPTOUI>
751+
m_GFPToUI(const SrcTy &Src) {
752+
return UnaryOp_match<SrcTy, TargetOpcode::G_FPTOUI>(Src);
753+
}
754+
743755
template <typename SrcTy>
744756
inline UnaryOp_match<SrcTy, TargetOpcode::G_FABS> m_GFabs(const SrcTy &Src) {
745757
return UnaryOp_match<SrcTy, TargetOpcode::G_FABS>(Src);

‎llvm/include/llvm/Target/GlobalISel/Combine.td‎

Lines changed: 27 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1243,6 +1243,32 @@ def mulh_to_lshr : GICombineRule<
12431243

12441244
def mulh_combines : GICombineGroup<[mulh_to_lshr]>;
12451245

1246+
def trunc_ssats : GICombineRule<
1247+
(defs root:$root, register_matchinfo:$matchinfo),
1248+
(match (G_TRUNC $dst, $src):$root,
1249+
[{ return Helper.matchTruncSSatS(*${root}, ${matchinfo}); }]),
1250+
(apply [{ Helper.applyTruncSSatS(*${root}, ${matchinfo}); }])>;
1251+
1252+
def trunc_ssatu : GICombineRule<
1253+
(defs root:$root, register_matchinfo:$matchinfo),
1254+
(match (G_TRUNC $dst, $src):$root,
1255+
[{ return Helper.matchTruncSSatU(*${root}, ${matchinfo}); }]),
1256+
(apply [{ Helper.applyTruncSSatU(*${root}, ${matchinfo}); }])>;
1257+
1258+
def trunc_usatu : GICombineRule<
1259+
(defs root:$root, register_matchinfo:$matchinfo),
1260+
(match (G_TRUNC $dst, $src):$root,
1261+
[{ return Helper.matchTruncUSatU(*${root}, ${matchinfo}); }]),
1262+
(apply [{ Helper.applyTruncUSatU(*${root}, ${matchinfo}); }])>;
1263+
1264+
def truncusatu_to_fptouisat : GICombineRule<
1265+
(defs root:$root, register_matchinfo:$matchinfo),
1266+
(match (G_TRUNC_USAT_U $dst, $src):$root,
1267+
[{ return Helper.matchTruncUSatUToFPTOUISat(*${root}, ${matchinfo}); }]),
1268+
(apply [{ Helper.applyTruncUSatUToFPTOUISat(*${root}, ${matchinfo}); }])>;
1269+
1270+
def truncsat_combines : GICombineGroup<[trunc_ssats, trunc_ssatu, trunc_usatu, truncusatu_to_fptouisat]>;
1271+
12461272
def redundant_neg_operands: GICombineRule<
12471273
(defs root:$root, build_fn_matchinfo:$matchinfo),
12481274
(match (wip_match_opcode G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMAD, G_FMA):$root,
@@ -2067,7 +2093,7 @@ def all_combines : GICombineGroup<[integer_reassoc_combines, trivial_combines,
20672093
fsub_to_fneg, commute_constant_to_rhs, match_ands, match_ors,
20682094
simplify_neg_minmax, combine_concat_vector,
20692095
sext_trunc, zext_trunc, prefer_sign_combines, shuffle_combines,
2070-
combine_use_vector_truncate, merge_combines, overflow_combines]>;
2096+
combine_use_vector_truncate, merge_combines, overflow_combines, truncsat_combines]>;
20712097

20722098
// A combine group used to for prelegalizer combiners at -O0. The combines in
20732099
// this group have been selected based on experiments to balance code size and

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp‎

Lines changed: 128 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5924,6 +5924,134 @@ void CombinerHelper::applyUMulHToLShr(MachineInstr &MI) const {
59245924
MI.eraseFromParent();
59255925
}
59265926

5927+
bool CombinerHelper::matchTruncSSatS(MachineInstr &MI,
5928+
Register &MatchInfo) const {
5929+
Register Dst = MI.getOperand(0).getReg();
5930+
Register Src = MI.getOperand(1).getReg();
5931+
LLT DstTy = MRI.getType(Dst);
5932+
LLT SrcTy = MRI.getType(Src);
5933+
unsigned NumDstBits = DstTy.getScalarSizeInBits();
5934+
unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
5935+
assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
5936+
5937+
APInt MinConst, MaxConst;
5938+
APInt SignedMax = APInt::getSignedMaxValue(NumDstBits).sext(NumSrcBits);
5939+
APInt SignedMin = APInt::getSignedMinValue(NumDstBits).sext(NumSrcBits);
5940+
5941+
if (isLegal({TargetOpcode::G_TRUNC_SSAT_S, {DstTy, SrcTy}})) {
5942+
if (mi_match(Src, MRI,
5943+
m_GSMin(m_GSMax(m_Reg(MatchInfo), m_ICstOrSplat(MinConst)),
5944+
m_ICstOrSplat(MaxConst))) &&
5945+
APInt::isSameValue(MinConst, SignedMin) &&
5946+
APInt::isSameValue(MaxConst, SignedMax))
5947+
return true;
5948+
if (mi_match(Src, MRI,
5949+
m_GSMax(m_GSMin(m_Reg(MatchInfo), m_ICstOrSplat(MaxConst)),
5950+
m_ICstOrSplat(MinConst))) &&
5951+
APInt::isSameValue(MinConst, SignedMin) &&
5952+
APInt::isSameValue(MaxConst, SignedMax))
5953+
return true;
5954+
}
5955+
return false;
5956+
}
5957+
5958+
void CombinerHelper::applyTruncSSatS(MachineInstr &MI,
5959+
Register &MatchInfo) const {
5960+
Register Dst = MI.getOperand(0).getReg();
5961+
Builder.buildTruncSSatS(Dst, MatchInfo);
5962+
MI.eraseFromParent();
5963+
}
5964+
5965+
bool CombinerHelper::matchTruncSSatU(MachineInstr &MI,
5966+
Register &MatchInfo) const {
5967+
Register Dst = MI.getOperand(0).getReg();
5968+
Register Src = MI.getOperand(1).getReg();
5969+
LLT DstTy = MRI.getType(Dst);
5970+
LLT SrcTy = MRI.getType(Src);
5971+
unsigned NumDstBits = DstTy.getScalarSizeInBits();
5972+
unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
5973+
assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
5974+
5975+
APInt MaxConst;
5976+
APInt UnsignedMax = APInt::getMaxValue(NumDstBits).zext(NumSrcBits);
5977+
5978+
if (isLegal({TargetOpcode::G_TRUNC_SSAT_U, {DstTy, SrcTy}})) {
5979+
if (mi_match(Src, MRI,
5980+
m_GSMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(0)),
5981+
m_ICstOrSplat(MaxConst))) &&
5982+
APInt::isSameValue(MaxConst, UnsignedMax))
5983+
return true;
5984+
if (mi_match(Src, MRI,
5985+
m_GSMax(m_GSMin(m_Reg(MatchInfo), m_ICstOrSplat(MaxConst)),
5986+
m_SpecificICstOrSplat(0))) &&
5987+
APInt::isSameValue(MaxConst, UnsignedMax))
5988+
return true;
5989+
if (mi_match(Src, MRI,
5990+
m_GUMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(0)),
5991+
m_ICstOrSplat(MaxConst))) &&
5992+
APInt::isSameValue(MaxConst, UnsignedMax))
5993+
return true;
5994+
}
5995+
return false;
5996+
}
5997+
5998+
void CombinerHelper::applyTruncSSatU(MachineInstr &MI,
5999+
Register &MatchInfo) const {
6000+
Register Dst = MI.getOperand(0).getReg();
6001+
Builder.buildTruncSSatU(Dst, MatchInfo);
6002+
MI.eraseFromParent();
6003+
}
6004+
6005+
bool CombinerHelper::matchTruncUSatU(MachineInstr &MI,
6006+
Register &MatchInfo) const {
6007+
Register Dst = MI.getOperand(0).getReg();
6008+
Register Src = MI.getOperand(1).getReg();
6009+
LLT DstTy = MRI.getType(Dst);
6010+
LLT SrcTy = MRI.getType(Src);
6011+
unsigned NumDstBits = DstTy.getScalarSizeInBits();
6012+
unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
6013+
assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
6014+
6015+
APInt MaxConst;
6016+
APInt UnsignedMax = APInt::getMaxValue(NumDstBits).zext(NumSrcBits);
6017+
6018+
if (isLegal({TargetOpcode::G_TRUNC_SSAT_U, {DstTy, SrcTy}})) {
6019+
if (mi_match(Src, MRI,
6020+
m_GUMin(m_Reg(MatchInfo), m_ICstOrSplat(MaxConst))) &&
6021+
APInt::isSameValue(MaxConst, UnsignedMax))
6022+
return true;
6023+
}
6024+
return false;
6025+
}
6026+
6027+
void CombinerHelper::applyTruncUSatU(MachineInstr &MI,
6028+
Register &MatchInfo) const {
6029+
Register Dst = MI.getOperand(0).getReg();
6030+
Builder.buildTruncUSatU(Dst, MatchInfo);
6031+
MI.eraseFromParent();
6032+
}
6033+
6034+
bool CombinerHelper::matchTruncUSatUToFPTOUISat(MachineInstr &MI,
6035+
Register &MatchInfo) const {
6036+
Register Dst = MI.getOperand(0).getReg();
6037+
Register Src = MI.getOperand(1).getReg();
6038+
LLT DstTy = MRI.getType(Dst);
6039+
LLT SrcTy = MRI.getType(Src);
6040+
6041+
if (isLegalOrBeforeLegalizer({TargetOpcode::G_FPTOUI_SAT, {DstTy, SrcTy}})) {
6042+
if (mi_match(Src, MRI, m_GFPToUI((m_Reg(MatchInfo)))))
6043+
return true;
6044+
}
6045+
return false;
6046+
}
6047+
6048+
void CombinerHelper::applyTruncUSatUToFPTOUISat(MachineInstr &MI,
6049+
Register &MatchInfo) const {
6050+
Register Dst = MI.getOperand(0).getReg();
6051+
Builder.buildFPTOUI_SAT(Dst, MatchInfo);
6052+
MI.eraseFromParent();
6053+
}
6054+
59276055
bool CombinerHelper::matchRedundantNegOperands(MachineInstr &MI,
59286056
BuildFnTy &MatchInfo) const {
59296057
unsigned Opc = MI.getOpcode();

‎llvm/test/CodeGen/AArch64/truncsat.ll‎

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
4+
5+
6+
define <4 x i16> @ssats_1(<4 x i32> %x) {
7+
; CHECK-LABEL: ssats_1:
8+
; CHECK: // %bb.0: // %entry
9+
; CHECK-NEXT: sqxtn v0.4h, v0.4s
10+
; CHECK-NEXT: ret
11+
entry:
12+
%spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %x, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
13+
%spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
14+
%conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
15+
ret <4 x i16> %conv6
16+
}
17+
18+
define <4 x i16> @ssats_2(<4 x i32> %x) {
19+
; CHECK-LABEL: ssats_2:
20+
; CHECK: // %bb.0: // %entry
21+
; CHECK-NEXT: sqxtn v0.4h, v0.4s
22+
; CHECK-NEXT: ret
23+
entry:
24+
%spec.store.select = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
25+
%spec.store.select7 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
26+
%conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
27+
ret <4 x i16> %conv6
28+
}
29+
30+
define <4 x i16> @ssatu_1(<4 x i32> %x) {
31+
; CHECK-LABEL: ssatu_1:
32+
; CHECK: // %bb.0: // %entry
33+
; CHECK-NEXT: sqxtun v0.4h, v0.4s
34+
; CHECK-NEXT: ret
35+
entry:
36+
%spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %x, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
37+
%spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> zeroinitializer)
38+
%conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
39+
ret <4 x i16> %conv6
40+
}
41+
42+
define <4 x i16> @ssatu_2(<4 x i32> %x) {
43+
; CHECK-LABEL: ssatu_2:
44+
; CHECK: // %bb.0: // %entry
45+
; CHECK-NEXT: sqxtun v0.4h, v0.4s
46+
; CHECK-NEXT: ret
47+
entry:
48+
%spec.store.select = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> zeroinitializer)
49+
%spec.store.select7 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
50+
%conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
51+
ret <4 x i16> %conv6
52+
}
53+
54+
define <4 x i16> @ssatu_3(<4 x i32> %x) {
55+
; CHECK-LABEL: ssatu_3:
56+
; CHECK: // %bb.0: // %entry
57+
; CHECK-NEXT: sqxtun v0.4h, v0.4s
58+
; CHECK-NEXT: ret
59+
entry:
60+
%spec.store.select = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> zeroinitializer)
61+
%spec.store.select7 = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
62+
%conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
63+
ret <4 x i16> %conv6
64+
}
65+
66+
define <4 x i16> @usatu(<4 x i32> %x) {
67+
; CHECK-LABEL: usatu:
68+
; CHECK: // %bb.0: // %entry
69+
; CHECK-NEXT: uqxtn v0.4h, v0.4s
70+
; CHECK-NEXT: ret
71+
entry:
72+
%spec.store.select = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %x, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
73+
%conv6 = trunc <4 x i32> %spec.store.select to <4 x i16>
74+
ret <4 x i16> %conv6
75+
}
76+
77+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
78+
; CHECK-GI: {{.*}}
79+
; CHECK-SD: {{.*}}

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