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Add docs and fixme
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llvm/docs/AMDGPUUsage.rst

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@@ -1828,6 +1828,20 @@ The AMDGPU backend supports the following calling conventions:
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..TODO::
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Describe.
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``amdgpu_gfx_whole_wave`` Used for AMD graphics targets. Functions with this calling convention
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cannot be used as entry points. They must have an i1 as the first argument,
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which will be mapped to the value of EXEC on entry into the function. Other
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arguments will contain poison in their inactive lanes. Similarly, the return
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value for the inactive lanes is poison.
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The function will run with all lanes enabled, i.e. EXEC will be set to -1 in the
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prologue and restored to its original value in the epilogue. The inactive lanes
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will be preserved for all the registers used by the function. Active lanes only
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will only be preserved for the callee saved registers.
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In all other respects, functions with this calling convention behave like
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``amdgpu_gfx`` functions.
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``amdgpu_gs`` Used for Mesa/AMDPAL geometry shaders.
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..TODO::
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Describe.

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

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@@ -1718,6 +1718,8 @@ void SIFrameLowering::determineCalleeSaves(MachineFunction &MF,
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// least their inactive lanes. Add them to WWMReservedRegs.
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assert(!NeedExecCopyReservedReg &&
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"Whole wave functions can use the reg mapped for their i1 argument");
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// FIXME: Be more efficient!
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for (MCRegister Reg : AMDGPU::VGPR_32RegClass)
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if (MF.getRegInfo().isPhysRegModified(Reg)) {
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MFI->reserveWWMRegister(Reg);

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