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[AArch64] Add intrinsics for SME FP8 FVDOT, FVDOTB and FVDOTT intrinsics
Add support for the following SME 8 bit floating-point dot-product intrinsics: ``` // Only if __ARM_FEATURE_SME_F8F16 != 0 void svvdot_lane_za16[_mf8]_vg1x2_fpm(uint32_t slice, svmfloat8x2_t zn, svmfloat8_t zm, uint64_t imm_idx, fpm_t fpm) __arm_streaming __arm_inout("za"); // Only if __ARM_FEATURE_SME_F8F32 != 0 void svvdott_lane_za32[_mf8]_vg1x4_fpm(uint32_t slice, svmfloat8x2_t zn, svmfloat8_t zm, uint64_t imm_idx, fpm_t fpm) __arm_streaming __arm_inout("za"); void svvdotb_lane_za32[_mf8]_vg1x4_fpm(uint32_t slice, svmfloat8x2_t zn, svmfloat8_t zm, uint64_t imm_idx, fpm_t fpm) __arm_streaming __arm_inout("za"); ``` Co-authored-by: Momchil Velikov <[email protected]> Co-authored-by: Marian Lukac <[email protected]>
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‎clang/include/clang/Basic/arm_sme.td‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -748,11 +748,16 @@ let SMETargetGuard = "sme2" in {
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let SMETargetGuard = "sme-f8f32" in {
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def SVDOT_LANE_FP8_ZA32_VG1x2 : Inst<"svdot_lane_za32[_mf8]_vg1x2_fpm", "vm2di>", "m", MergeNone, "aarch64_sme_fp8_fdot_lane_za32_vg1x2", [IsStreaming, IsInOutZA, SetsFPMR, IsOverloadNone], [ImmCheck<3, ImmCheck0_3>]>;
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def SVDOT_LANE_FP8_ZA32_VG1x4 : Inst<"svdot_lane_za32[_mf8]_vg1x4_fpm", "vm4di>", "m", MergeNone, "aarch64_sme_fp8_fdot_lane_za32_vg1x4", [IsStreaming, IsInOutZA, SetsFPMR, IsOverloadNone], [ImmCheck<3, ImmCheck0_3>]>;
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def SVVDOTB_LANE_FP8_ZA32_VG1x4 : Inst<"svvdotb_lane_za32[_f8]_vg1x4", "vm2di>", "m", MergeNone, "aarch64_sme_fp8_fvdotb_lane_za32_vg1x4", [IsOverloadNone, IsStreaming, IsInOutZA, SetsFPMR], [ImmCheck<3, ImmCheck0_3>]>;
753+
def SVVDOTT_LANE_FP8_ZA32_VG1x4 : Inst<"svvdott_lane_za32[_f8]_vg1x4", "vm2di>", "m", MergeNone, "aarch64_sme_fp8_fvdott_lane_za32_vg1x4", [IsOverloadNone, IsStreaming, IsInOutZA, SetsFPMR], [ImmCheck<3, ImmCheck0_3>]>;
751754
}
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let SMETargetGuard = "sme-f8f16" in {
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def SVDOT_LANE_FP8_ZA16_VG1x2 : Inst<"svdot_lane_za16[_mf8]_vg1x2_fpm", "vm2di>", "m", MergeNone, "aarch64_sme_fp8_fdot_lane_za16_vg1x2", [IsStreaming, IsInOutZA, SetsFPMR, IsOverloadNone], [ImmCheck<3, ImmCheck0_7>]>;
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def SVDOT_LANE_FP8_ZA16_VG1x4 : Inst<"svdot_lane_za16[_mf8]_vg1x4_fpm", "vm4di>", "m", MergeNone, "aarch64_sme_fp8_fdot_lane_za16_vg1x4", [IsStreaming, IsInOutZA, SetsFPMR, IsOverloadNone], [ImmCheck<3, ImmCheck0_7>]>;
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def SVVDOT_LANE_FP8_ZA16_VG1x2 : Inst<"svvdot_lane_za16[_f8]_vg1x2", "vm2di>", "m", MergeNone, "aarch64_sme_fp8_fvdot_lane_za16_vg1x2", [IsOverloadNone, IsStreaming, IsInOutZA, SetsFPMR], [ImmCheck<3, ImmCheck0_7>]>;
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}
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////////////////////////////////////////////////////////////////////////////////

‎clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c‎

Lines changed: 80 additions & 0 deletions
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@@ -0,0 +1,80 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
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// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s
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// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
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// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s
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// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
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// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f8f16 -target-feature +sme-f8f32 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
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// REQUIRES: aarch64-registered-target
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#include <arm_sme.h>
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#ifdef SVE_OVERLOADED_FORMS
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#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3) A1##A3
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#else
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#define SVE_ACLE_FUNC(A1, A2, A3) A1##A2##A3
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#endif
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// CHECK-LABEL: define dso_local void @test_svvdot_lane_za16_f8_vg1x2(
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// CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]], i32 7)
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// CHECK-NEXT: ret void
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//
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// CPP-CHECK-LABEL: define dso_local void @_Z30test_svvdot_lane_za16_f8_vg1x2j13svmfloat8x2_tu13__SVMfloat8_tm(
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// CPP-CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0:[0-9]+]] {
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
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// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]], i32 7)
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// CPP-CHECK-NEXT: ret void
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//
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void test_svvdot_lane_za16_f8_vg1x2(uint32_t slice, svmfloat8x2_t zn,
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svmfloat8_t zm,
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fpm_t fpmr) __arm_streaming
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__arm_inout("za") {
37+
SVE_ACLE_FUNC(svvdot_lane_za16, _f8, _vg1x2)(slice, zn, zm, 7, fpmr);
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}
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// CHECK-LABEL: define dso_local void @test_svvdotb_lane_za32_f8_vg1x4(
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// CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]], i32 3)
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// CHECK-NEXT: ret void
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//
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// CPP-CHECK-LABEL: define dso_local void @_Z31test_svvdotb_lane_za32_f8_vg1x4j13svmfloat8x2_tu13__SVMfloat8_tm(
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// CPP-CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
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// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]], i32 3)
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// CPP-CHECK-NEXT: ret void
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//
54+
void test_svvdotb_lane_za32_f8_vg1x4(uint32_t slice, svmfloat8x2_t zn,
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svmfloat8_t zm,
56+
fpm_t fpmr) __arm_streaming
57+
__arm_inout("za") {
58+
SVE_ACLE_FUNC(svvdotb_lane_za32, _f8, _vg1x4)(slice, zn, zm, 3, fpmr);
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}
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// CHECK-LABEL: define dso_local void @test_svvdott_lane_za32_f8_vg1x4(
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// CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
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// CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]], i32 3)
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// CHECK-NEXT: ret void
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//
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// CPP-CHECK-LABEL: define dso_local void @_Z31test_svvdott_lane_za32_f8_vg1x4j13svmfloat8x2_tu13__SVMfloat8_tm(
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// CPP-CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
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// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32 [[SLICE]], <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]], i32 3)
73+
// CPP-CHECK-NEXT: ret void
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//
75+
void test_svvdott_lane_za32_f8_vg1x4(uint32_t slice, svmfloat8x2_t zn,
76+
svmfloat8_t zm,
77+
fpm_t fpmr) __arm_streaming
78+
__arm_inout("za") {
79+
SVE_ACLE_FUNC(svvdott_lane_za32, _f8, _vg1x4)(slice, zn, zm, 3, fpmr);
80+
}

‎clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fp8_fvdot.c‎

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@@ -0,0 +1,32 @@
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -verify -emit-llvm -o - %s
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// REQUIRES: aarch64-registered-target
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#include <arm_sme.h>
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void test_features(uint32_t slice, fpm_t fpmr, svmfloat8x2_t zn,
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svmfloat8_t zm) __arm_streaming __arm_inout("za") {
9+
// expected-error@+1 {{'svvdot_lane_za16_f8_vg1x2' needs target feature sme,sme-f8f16}}
10+
svvdot_lane_za16_f8_vg1x2(slice, zn, zm, 7, fpmr);
11+
// expected-error@+1 {{'svvdotb_lane_za32_f8_vg1x4' needs target feature sme,sme-f8f32}}
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svvdotb_lane_za32_f8_vg1x4(slice, zn, zm, 3, fpmr);
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// expected-error@+1 {{'svvdott_lane_za32_f8_vg1x4' needs target feature sme,sme-f8f32}}
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svvdott_lane_za32_f8_vg1x4(slice, zn, zm, 3, fpmr);
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}
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void test_imm(uint32_t slice, fpm_t fpmr, svmfloat8x2_t zn,
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svmfloat8_t zm) __arm_streaming __arm_inout("za") {
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// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}}
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svvdot_lane_za16_f8_vg1x2(slice, zn, zm, -1, fpmr);
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// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
22+
svvdotb_lane_za32_f8_vg1x4(slice, zn, zm, -1, fpmr);
23+
// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
24+
svvdott_lane_za32_f8_vg1x4(slice, zn, zm, -1, fpmr);
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// expected-error@+1{{argument value 8 is outside the valid range [0, 7]}}
27+
svvdot_lane_za16_f8_vg1x2(slice, zn, zm, 8, fpmr);
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// expected-error@+1{{argument value 4 is outside the valid range [0, 3]}}
29+
svvdotb_lane_za32_f8_vg1x4(slice, zn, zm, 4, fpmr);
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// expected-error@+1{{argument value 4 is outside the valid range [0, 3]}}
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svvdott_lane_za32_f8_vg1x4(slice, zn, zm, 4, fpmr);
32+
}

‎llvm/include/llvm/IR/IntrinsicsAArch64.td‎

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Original file line numberDiff line numberDiff line change
@@ -3879,6 +3879,11 @@ class SME2_FP8_FDOT_LANE_VG1x4 :
38793879

38803880
def int_aarch64_sme_fp8_fdot_lane_za32_vg1x2 : SME2_FP8_FDOT_LANE_VG1x2;
38813881
def int_aarch64_sme_fp8_fdot_lane_za32_vg1x4 : SME2_FP8_FDOT_LANE_VG1x4;
3882+
3883+
def int_aarch64_sme_fp8_fvdot_lane_za16_vg1x2 : SME2_FP8_FDOT_LANE_VG1x2;
3884+
3885+
def int_aarch64_sme_fp8_fvdotb_lane_za32_vg1x4 : SME2_FP8_FDOT_LANE_VG1x2;
3886+
def int_aarch64_sme_fp8_fvdott_lane_za32_vg1x4 : SME2_FP8_FDOT_LANE_VG1x2;
38823887
}
38833888

38843889
//

‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -985,8 +985,8 @@ def LUTI4_S_4ZZT2Z : sme2_luti4_vector_vg4_strided<0b00, 0b00, "luti4">;
985985
} //[HasSME2p1, HasSME_LUTv2]
986986

987987
let Predicates = [HasSMEF8F16] in {
988-
defm FVDOT_VG2_M2ZZI_BtoH : sme2p1_multi_vec_array_vg2_index_f8f16<"fvdot", 0b11, 0b110, ZZ_b_mul_r, ZPR4b8>;
989-
defm FDOT_VG2_M2ZZI_BtoH : sme2_fp8_fdot_index_za16_vg1x2<"fdot", int_aarch64_sme_fp8_fdot_lane_za16_vg1x2>;
988+
defm FVDOT_VG2_M2ZZI_BtoH : sme2_fp8_fdot_index_za16_vg1x2<"fvdot", 0b110, int_aarch64_sme_fp8_fvdot_lane_za16_vg1x2>;
989+
defm FDOT_VG2_M2ZZI_BtoH : sme2_fp8_fdot_index_za16_vg1x2<"fdot", 0b010, int_aarch64_sme_fp8_fdot_lane_za16_vg1x2>;
990990
defm FDOT_VG4_M4ZZI_BtoH : sme2_fp8_fdot_index_za16_vg1x4<"fdot", int_aarch64_sme_fp8_fdot_lane_za16_vg1x4>;
991991
defm FDOT_VG2_M2ZZ_BtoH : sme2_dot_mla_add_sub_array_vg24_single<"fdot", 0b0010001, MatrixOp16, ZZ_b, ZPR4b8>;
992992
defm FDOT_VG4_M4ZZ_BtoH : sme2_dot_mla_add_sub_array_vg24_single<"fdot", 0b0110001, MatrixOp16, ZZZZ_b, ZPR4b8>;
@@ -1017,8 +1017,8 @@ defm FDOT_VG4_M4ZZ_BtoS : sme2_dot_mla_add_sub_array_vg24_single<"fdot", 0b0110
10171017
defm FDOT_VG2_M2Z2Z_BtoS : sme2_dot_mla_add_sub_array_vg2_multi<"fdot", 0b0100110, MatrixOp32, ZZ_b_mul_r, nxv16i8, null_frag>;
10181018
defm FDOT_VG4_M4Z4Z_BtoS : sme2_dot_mla_add_sub_array_vg4_multi<"fdot", 0b0100110, MatrixOp32, ZZZZ_b_mul_r, nxv16i8, null_frag>;
10191019

1020-
def FVDOTB_VG4_M2ZZI_BtoS : sme2_fp8_multi_vec_array_vg4_index<"fvdotb", 0b0>;
1021-
def FVDOTT_VG4_M2ZZI_BtoS : sme2_fp8_multi_vec_array_vg4_index<"fvdott", 0b1>;
1020+
defm FVDOTB_VG4_M2ZZI_BtoS : sme2_fp8_fdotv_index_za32_vg1x4<"fvdotb", 0b0, int_aarch64_sme_fp8_fvdotb_lane_za32_vg1x4>;
1021+
defm FVDOTT_VG4_M2ZZI_BtoS : sme2_fp8_fdotv_index_za32_vg1x4<"fvdott", 0b1, int_aarch64_sme_fp8_fvdott_lane_za32_vg1x4>;
10221022

10231023
defm FMLALL_MZZI_BtoS : sme2_mla_ll_array_index_32b<"fmlall", 0b01, 0b000, null_frag>;
10241024
defm FMLALL_VG2_M2ZZI_BtoS : sme2_mla_ll_array_vg2_index_32b<"fmlall", 0b10, 0b100, null_frag>;

‎llvm/lib/Target/AArch64/SMEInstrFormats.td‎

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5797,9 +5797,9 @@ multiclass sme2_fmop4a_fp8_fp16_2way<string mnemonic> {
57975797

57985798
// FP8 SME FDOT instructions
57995799

5800-
multiclass sme2_fp8_fdot_index_za16_vg1x2<string mnemonic,
5800+
multiclass sme2_fp8_fdot_index_za16_vg1x2<string mnemonic, bits<3> op,
58015801
SDPatternOperator intrinsic> {
5802-
def NAME : sme2_multi_vec_array_vg2_index<0b11, {0b0,?,?,0b10,?}, MatrixOp16,
5802+
def NAME : sme2_multi_vec_array_vg2_index<0b11, {op{2},?,?,op{1-0},?}, MatrixOp16,
58035803
ZZ_b_mul_r, ZPR4b8,
58045804
VectorIndexH32b_timm, mnemonic>,
58055805
SMEPseudo2Instr<NAME, 1>{
@@ -5882,3 +5882,14 @@ multiclass sme2_fp8_fdot_index_za32_vg1x4<string mnemonic,
58825882

58835883
def : SME2_ZA_TwoOp_VG4_Multi_Index_Pat<NAME, intrinsic, sme_elm_idx0_7, ZPR4b8, nxv16i8, VectorIndexS32b_timm, tileslice16>;
58845884
}
5885+
5886+
multiclass sme2_fp8_fdotv_index_za32_vg1x4<string mnemonic, bit T, SDPatternOperator intrinsic> {
5887+
def NAME : sme2_fp8_multi_vec_array_vg4_index<mnemonic, T>,
5888+
SMEPseudo2Instr<NAME, 1> {
5889+
let Uses=[FPMR, FPCR];
5890+
}
5891+
5892+
def _PSEUDO : sme2_za_array_2op_multi_index_pseudo<NAME, sme_elm_idx0_7, ZZ_b_mul_r, ZPR4b8, VectorIndexS32b_timm, SMEMatrixArray>;
5893+
5894+
def : SME2_ZA_TwoOp_VG2_Multi_Index_Pat<NAME, intrinsic, sme_elm_idx0_7, ZPR4b8, nxv16i8, VectorIndexH32b_timm, tileslice16>;
5895+
}

‎llvm/test/CodeGen/AArch64/sme2-intrinsics-fp8-fvdot.ll‎

Lines changed: 54 additions & 0 deletions
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@@ -0,0 +1,54 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "// kill:" --version 4
2+
; RUN: llc -force-streaming < %s | FileCheck %s
3+
target triple = "aarch64-linux"
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define void @test_fvdot16_1x2_indexed(i32 %slice.0,
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; CHECK-LABEL: test_fvdot16_1x2_indexed:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fvdot za.h[w8, 7, vgx2], { z0.b, z1.b }, z2.b[3]
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; CHECK: ret
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm) #0 {
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%slice = add i32 %slice.0, 7
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call void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32 %slice,
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm, i32 3)
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ret void
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}
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define void @test_fvdot32_bottom_1x4_indexed(i32 %slice.0,
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; CHECK-LABEL: test_fvdot32_bottom_1x4_indexed:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fvdotb za.s[w8, 7, vgx4], { z0.b, z1.b }, z2.b[3]
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; CHECK: ret
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm) #0 {
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%slice = add i32 %slice.0, 7
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call void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32 %slice,
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm, i32 3)
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ret void
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}
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define void @test_fvdot32_top_1x4_indexed(i32 %slice.0,
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; CHECK-LABEL: test_fvdot32_top_1x4_indexed:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fvdott za.s[w8, 7, vgx4], { z0.b, z1.b }, z2.b[3]
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; CHECK: ret
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm) #0 {
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%slice = add i32 %slice.0, 7
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call void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32 %slice,
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm, i32 3)
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ret void
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}
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declare void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32)
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declare void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32)
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declare void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32)
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attributes #0 = { "target-features" = "+sme-f8f32,+sme-f8f16" }

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