Fix f16 Zicond SELECT lowering with Zhinx

Author: fennecJ

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -9565,6 +9565,9 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
     MVT XLenIntVT = Subtarget.getXLenVT();
 
     auto CastToInt = [&](SDValue V) -> SDValue {
+      if (VT == MVT::f16) {
+        return DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, XLenIntVT, V);
+      }
       if (VT == MVT::f32 && Subtarget.is64Bit()) {
         return DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, XLenIntVT, V);
       }
@@ -9582,6 +9585,9 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
     if (VT == MVT::f32 && Subtarget.is64Bit()) {
       return DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, VT, ResultInt);
     }
+    if (VT == MVT::f16) {
+      return DAG.getNode(RISCVISD::FMV_H_X, DL, VT, ResultInt);
+    }
     return DAG.getBitcast(VT, ResultInt);
   }