clang format

Author: hiraditya

llvm/lib/Target/RISCV/RISCVLiveVariables.cpp

@@ -101,6 +101,7 @@ class RISCVLiveVariables : public MachineFunctionPass {
   void print(raw_ostream &OS, const Module *M = nullptr) const override;
 
   void verifyLiveness(MachineFunction &MF) const;
+
 private:
   /// Compute local liveness information (Use and Def sets) for each block
   void computeLocalLiveness(MachineFunction &MF);
@@ -160,8 +161,8 @@ bool RISCVLiveVariables::isTrackableRegister(
 }
 
 void RISCVLiveVariables::processInstruction(const MachineInstr &MI,
-                                             LivenessInfo &Info,
-                                             const TargetRegisterInfo *TRI) {
+                                            LivenessInfo &Info,
+                                            const TargetRegisterInfo *TRI) {
   std::vector<Register> GenVec;
   for (const MachineOperand &MO : MI.operands()) {
     if (!MO.isReg() || !MO.getReg())
@@ -174,7 +175,8 @@ void RISCVLiveVariables::processInstruction(const MachineInstr &MI,
       continue;
 
     if (MO.isUse()) {
-      // This is a use - only add to Use set if not already defined in this block
+      // This is a use - only add to Use set if not already defined in this
+      // block
       if (Info.Gen.find(Reg) == Info.Gen.end()) {
         Info.Use.insert(Reg);
 
@@ -205,8 +207,8 @@ void RISCVLiveVariables::processInstruction(const MachineInstr &MI,
     Info.Gen.insert(Reg);
     if (Reg.isPhysical()) {
       for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/false);
-                SubRegs.isValid(); ++SubRegs) {
-            Info.Gen.insert(*SubRegs);
+           SubRegs.isValid(); ++SubRegs) {
+        Info.Gen.insert(*SubRegs);
       }
     }
   }
@@ -324,8 +326,7 @@ void RISCVLiveVariables::computeGlobalLiveness(MachineFunction &MF) {
   }
 }
 
-bool RISCVLiveVariables::isLiveAt(Register Reg,
-                                   const MachineInstr &MI) const {
+bool RISCVLiveVariables::isLiveAt(Register Reg, const MachineInstr &MI) const {
   const MachineBasicBlock *MBB = MI.getParent();
   auto It = BlockLiveness.find(MBB);
 

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

@@ -103,10 +103,10 @@ static cl::opt<bool>
                            cl::desc("Enable Machine Pipeliner for RISC-V"),
                            cl::init(false), cl::Hidden);
 
-static cl::opt<bool>
-EnableRISCVLiveVariables("riscv-live-variables",
-                         cl::desc("Enable Live Variable Analysis for RISC-V"),
-                         cl::init(false), cl::Hidden);
+static cl::opt<bool> EnableRISCVLiveVariables(
+    "riscv-enable-live-variables",
+    cl::desc("Enable Live Variable Analysis for RISC-V"), cl::init(false),
+    cl::Hidden);
 
 extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());

llvm/test/CodeGen/RISCV/machine-live-variables.mir

@@ -1,18 +1,13 @@
-# RUN: llc -mtriple=riscv64 -verify-machineinstrs -run-pass=riscv-live-variables -debug < %s | FileCheck %s
+# RUN: llc -x mir -mtriple=riscv64 -verify-machineinstrs -run-pass=riscv-live-variables -debug < %s 2>&1 \
+# RUN: | FileCheck %s
 
 # REQUIRES: asserts
 
-;CHECK: Block:  (Number: 1)
-;CHECK:   Live-In:  { }
-;CHECK:   Live-Out: { }
-;CHECK:   Use:      { }
-;CHECK:   Def:      { $x10 $x11 $x12 $x13 $x14 $x15 $x16 $x10_h $x11_h $x12_h $x13_h $x14_h $x15_h $x16_h $x10_w $x11_w $x12_w $x13_w $x14_w $x15_w $x16_w }
-;CHECK: 
-;CHECK: Block:  (Number: 0)
-;CHECK:   Live-In:  { $x11 $x12 $x13 $x14 $x15 $x16 $x17 $x11_h $x12_h $x13_h $x14_h $x15_h $x16_h $x17_h $x11_w $x12_w $x13_w $x14_w $x15_w $x16_w $x17_w }
-;CHECK:   Live-Out: { }
-;CHECK:   Use:      { $x11 $x12 $x13 $x14 $x15 $x16 $x17 $x11_h $x12_h $x13_h $x14_h $x15_h $x16_h $x17_h $x11_w $x12_w $x13_w $x14_w $x15_w $x16_w $x17_w }
-;CHECK:   Def:      { $x10 $x11 $x12 $x10_h $x11_h $x12_h $x10_w $x11_w $x12_w }
+# CHECK: Block: (Number: 0)
+# CHECK:   Live-In:  { $x11 $x12 $x13 $x14 $x15 $x16 $x17 $x11_h $x12_h $x13_h $x14_h $x15_h $x16_h $x17_h $x11_w $x12_w $x13_w $x14_w $x15_w $x16_w $x17_w }
+# CHECK:   Live-Out: { }
+# CHECK:   Use:      { $x11 $x12 $x13 $x14 $x15 $x16 $x17 $x11_h $x12_h $x13_h $x14_h $x15_h $x16_h $x17_h $x11_w $x12_w $x13_w $x14_w $x15_w $x16_w $x17_w }
+# CHECK:   Def:      { $x10 $x11 $x12 $x10_h $x11_h $x12_h $x10_w $x11_w $x12_w }
 
 --- |
 
@@ -77,3 +72,5 @@ body: |
     SW killed renamable $x12, %stack.0.va, 4 :: (store (s32) into %ir.va + 4)
     renamable $x10 = LW killed renamable $x10, 0 :: (load (s32) from %ir.argp.cur)
     PseudoRET implicit $x10
+
+...