comments + refactoring

Author: apeskov

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -10974,8 +10974,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
 
   // fold (srl (or x, (shl (zext y), c1)), c1) -> (or (srl x, c1), (zext y))
   // c1 <= leadingzeros(zext(y))
-  if (N1C && (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND ||
-              N0.getOpcode() == ISD::XOR)) {
+  if (N1C && ISD::isBitwiseLogicOp(N0.getOpcode())) {
     SDValue lhs = N0.getOperand(0);
     SDValue rhs = N0.getOperand(1);
     SDValue shl;
@@ -10987,19 +10986,17 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
       shl = rhs;
       other = lhs;
     }
-    if (shl.getNode()) {
-      if (shl.getOperand(1).getNode() == N1C) {
-        SDValue zext = shl.getOperand(0);
-        if (zext.getOpcode() == ISD::ZERO_EXTEND) {
-          unsigned numLeadingZeros =
-              zext.getValueType().getSizeInBits() -
-              zext.getOperand(0).getValueType().getSizeInBits();
-          if (N1C->getZExtValue() <= numLeadingZeros) {
-            return DAG.getNode(
-                N0.getOpcode(), SDLoc(N0), VT,
-                DAG.getNode(ISD::SRL, SDLoc(N0), VT, other, SDValue(N1C, 0)),
-                zext);
-          }
+    if (shl && shl.getOperand(1) == N1) {
+      SDValue zext = shl.getOperand(0);
+      if (zext.getOpcode() == ISD::ZERO_EXTEND) {
+        unsigned numLeadingZeros =
+            zext.getValueType().getScalarSizeInBits() -
+            zext.getOperand(0).getValueType().getScalarSizeInBits();
+        if (N1C->getZExtValue() <= numLeadingZeros) {
+          return DAG.getNode(
+              N0.getOpcode(), SDLoc(N0), VT,
+              DAG.getNode(ISD::SRL, SDLoc(N0), VT, other, SDValue(N1C, 0)),
+              zext);
         }
       }
     }

llvm/test/CodeGen/NVPTX/shift-opt.ll

@@ -1,16 +1,16 @@
 ; RUN: llc < %s -mtriple=nvptx64 | FileCheck %s
 
-define i64 @test1(i64 %x, i32 %y) {
+define i64 @test_or(i64 %x, i32 %y) {
 ;
 ; srl (or (x, shl(zext(y),c1)),c1) -> or(srl(x,c1), zext(y))
 ; c1 <= leadingzeros(zext(y))
 ;
-; CHECK-LABEL: test1
-; CHECK: ld.param.u64 %[[X:rd[0-9]+]], [test1_param_0];
-; CHECK: ld.param.u32 %[[Y:rd[0-9]+]], [test1_param_1];
+; CHECK-LABEL: test_or
+; CHECK: ld.param.u64 %[[X:rd[0-9]+]], [test_or_param_0];
+; CHECK: ld.param.u32 %[[Y:rd[0-9]+]], [test_or_param_1];
 ; CHECK: shr.u64      %[[SHR:rd[0-9]+]], %[[X]], 5;
-; CHECK: or.b64       %[[OR:rd[0-9]+]], %[[SHR]], %[[Y]];
-; CHECK: st.param.b64 [func_retval0], %[[OR]];
+; CHECK: or.b64       %[[LOP:rd[0-9]+]], %[[SHR]], %[[Y]];
+; CHECK: st.param.b64 [func_retval0], %[[LOP]];
 ;
   %ext = zext i32 %y to i64
   %shl = shl i64 %ext, 5
@@ -19,6 +19,63 @@ define i64 @test1(i64 %x, i32 %y) {
   ret i64 %srl
 }
 
+define i64 @test_xor(i64 %x, i32 %y) {
+;
+; srl (xor (x, shl(zext(y),c1)),c1) -> xor(srl(x,c1), zext(y))
+; c1 <= leadingzeros(zext(y))
+;
+; CHECK-LABEL: test_xor
+; CHECK: ld.param.u64 %[[X:rd[0-9]+]], [test_xor_param_0];
+; CHECK: ld.param.u32 %[[Y:rd[0-9]+]], [test_xor_param_1];
+; CHECK: shr.u64      %[[SHR:rd[0-9]+]], %[[X]], 5;
+; CHECK: xor.b64      %[[LOP:rd[0-9]+]], %[[SHR]], %[[Y]];
+; CHECK: st.param.b64 [func_retval0], %[[LOP]];
+;
+  %ext = zext i32 %y to i64
+  %shl = shl i64 %ext, 5
+  %or = xor i64 %x, %shl
+  %srl = lshr i64 %or, 5
+  ret i64 %srl
+}
+
+define i64 @test_and(i64 %x, i32 %y) {
+;
+; srl (and (x, shl(zext(y),c1)),c1) -> and(srl(x,c1), zext(y))
+; c1 <= leadingzeros(zext(y))
+;
+; CHECK-LABEL: test_and
+; CHECK: ld.param.u64 %[[X:rd[0-9]+]], [test_and_param_0];
+; CHECK: ld.param.u32 %[[Y:rd[0-9]+]], [test_and_param_1];
+; CHECK: shr.u64      %[[SHR:rd[0-9]+]], %[[X]], 5;
+; CHECK: and.b64      %[[LOP:rd[0-9]+]], %[[SHR]], %[[Y]];
+; CHECK: st.param.b64 [func_retval0], %[[LOP]];
+;
+  %ext = zext i32 %y to i64
+  %shl = shl i64 %ext, 5
+  %or = and i64 %x, %shl
+  %srl = lshr i64 %or, 5
+  ret i64 %srl
+}
+
+define <2 x i64> @test_or_vec(<2 x i64> %x, <2 x i32> %y) {
+;
+; srl (or (x, shl(zext(y),c1)),c1) -> or(srl(x,c1), zext(y))
+; c1 <= leadingzeros(zext(y))
+;
+; CHECK-LABEL: test_or
+; CHECK: ld.param.u64 %[[X:rd[0-9]+]], [test_or_param_0];
+; CHECK: ld.param.u32 %[[Y:rd[0-9]+]], [test_or_param_1];
+; CHECK: shr.u64      %[[SHR:rd[0-9]+]], %[[X]], 5;
+; CHECK: or.b64       %[[LOP:rd[0-9]+]], %[[SHR]], %[[Y]];
+; CHECK: st.param.b64 [func_retval0], %[[LOP]];
+;
+  %ext = zext <2 x i32> %y to <2 x i64>
+  %shl = shl <2 x i64> %ext, splat(i64 5)
+  %or = or <2 x i64> %x, %shl
+  %srl = lshr <2 x i64> %or, splat(i64 5)
+  ret <2 x i64> %srl
+}
+
 define i64 @test2(i64 %x, i32 %y) {
 ;
 ; srl (or (x, shl(zext(y),c1)),c1) -> or(srl(x,c1), zext(y))