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1 parent 129b7e4 commit e28c48cCopy full SHA for e28c48c
llvm/docs/CommandGuide/llvm-mca.rst
@@ -393,7 +393,7 @@ cache misses that impact load latencies. The syntax is like
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mov (%edi), %eax
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# LLVM-MCA-LATENCY
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-It set the latency of mov instruction to 100. LLVM-MCA-LATENCY without
+It sets the latency of mov instruction to 100. LLVM-MCA-LATENCY without
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argument ends the region with explicit latency, after it default target
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latencies are used.
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