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Restore deleted test
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‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir‎

Lines changed: 0 additions & 87 deletions
Original file line numberDiff line numberDiff line change
@@ -176,93 +176,6 @@ body: |
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%2:_(s32) = G_ADD %0, %1
177177
...
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---
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name: add_v2s16_ss
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: add_v2s16_ss
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
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; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>)
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32)
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; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>)
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; CHECK-NEXT: [[LSHR1:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
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; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[BITCAST]], [[BITCAST1]]
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; CHECK-NEXT: [[ADD1:%[0-9]+]]:sgpr(s32) = G_ADD [[LSHR]], [[LSHR1]]
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; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ADD]](s32), [[ADD1]](s32)
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; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR_TRUNC]](<2 x s16>)
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%0:_(<2 x s16>) = COPY $sgpr0
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%1:_(<2 x s16>) = COPY $sgpr1
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%2:_(<2 x s16>) = G_ADD %0, %1
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S_ENDPGM 0, implicit %2
204-
...
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---
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name: add_v2s16_sv
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; CHECK-LABEL: name: add_v2s16_sv
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; CHECK: liveins: $sgpr0, $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY]](<2 x s16>)
219-
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(<2 x s16>) = G_ADD [[COPY2]], [[COPY1]]
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; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](<2 x s16>)
221-
%0:_(<2 x s16>) = COPY $sgpr0
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%1:_(<2 x s16>) = COPY $vgpr0
223-
%2:_(<2 x s16>) = G_ADD %0, %1
224-
S_ENDPGM 0, implicit %2
225-
...
226-
227-
---
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name: add_v2s16_vs
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legalized: true
230-
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body: |
232-
bb.0:
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liveins: $sgpr0, $vgpr0
234-
; CHECK-LABEL: name: add_v2s16_vs
235-
; CHECK: liveins: $sgpr0, $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY1]](<2 x s16>)
240-
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(<2 x s16>) = G_ADD [[COPY]], [[COPY2]]
241-
%0:_(<2 x s16>) = COPY $vgpr0
242-
%1:_(<2 x s16>) = COPY $sgpr0
243-
%2:_(<2 x s16>) = G_ADD %0, %1
244-
...
245-
246-
---
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name: add_v2s16_vv
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legalized: true
249-
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body: |
251-
bb.0:
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liveins: $vgpr0, $vgpr1
253-
; CHECK-LABEL: name: add_v2s16_vv
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
257-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
258-
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(<2 x s16>) = G_ADD [[COPY]], [[COPY1]]
259-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](<2 x s16>)
260-
%0:_(<2 x s16>) = COPY $vgpr0
261-
%1:_(<2 x s16>) = COPY $vgpr1
262-
%2:_(<2 x s16>) = G_ADD %0, %1
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S_ENDPGM 0, implicit %2
264-
...
265-
266179
---
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name: add_s64_ss
268181
legalized: true

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir‎

Lines changed: 89 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,89 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
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---
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name: add_v2s16_ss
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legalized: true
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body: |
9+
bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: add_v2s16_ss
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
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; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>)
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32)
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; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>)
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; CHECK-NEXT: [[LSHR1:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
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; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[BITCAST]], [[BITCAST1]]
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; CHECK-NEXT: [[ADD1:%[0-9]+]]:sgpr(s32) = G_ADD [[LSHR]], [[LSHR1]]
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; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ADD]](s32), [[ADD1]](s32)
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; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR_TRUNC]](<2 x s16>)
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%0:_(<2 x s16>) = COPY $sgpr0
26+
%1:_(<2 x s16>) = COPY $sgpr1
27+
%2:_(<2 x s16>) = G_ADD %0, %1
28+
S_ENDPGM 0, implicit %2
29+
...
30+
31+
---
32+
name: add_v2s16_sv
33+
legalized: true
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body: |
36+
bb.0:
37+
liveins: $sgpr0, $vgpr0
38+
; CHECK-LABEL: name: add_v2s16_sv
39+
; CHECK: liveins: $sgpr0, $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY]](<2 x s16>)
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; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(<2 x s16>) = G_ADD [[COPY2]], [[COPY1]]
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; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](<2 x s16>)
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%0:_(<2 x s16>) = COPY $sgpr0
47+
%1:_(<2 x s16>) = COPY $vgpr0
48+
%2:_(<2 x s16>) = G_ADD %0, %1
49+
S_ENDPGM 0, implicit %2
50+
...
51+
52+
---
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name: add_v2s16_vs
54+
legalized: true
55+
56+
body: |
57+
bb.0:
58+
liveins: $sgpr0, $vgpr0
59+
; CHECK-LABEL: name: add_v2s16_vs
60+
; CHECK: liveins: $sgpr0, $vgpr0
61+
; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY1]](<2 x s16>)
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; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(<2 x s16>) = G_ADD [[COPY]], [[COPY2]]
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%0:_(<2 x s16>) = COPY $vgpr0
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%1:_(<2 x s16>) = COPY $sgpr0
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%2:_(<2 x s16>) = G_ADD %0, %1
69+
...
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---
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name: add_v2s16_vv
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legalized: true
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75+
body: |
76+
bb.0:
77+
liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: add_v2s16_vv
79+
; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
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; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(<2 x s16>) = G_ADD [[COPY]], [[COPY1]]
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; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](<2 x s16>)
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%0:_(<2 x s16>) = COPY $vgpr0
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%1:_(<2 x s16>) = COPY $vgpr1
87+
%2:_(<2 x s16>) = G_ADD %0, %1
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S_ENDPGM 0, implicit %2
89+
...

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