Update ARMISelLowering.cpp

Author: AZero13

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -20242,8 +20242,32 @@ static bool optimizeLogicalImm(SDValue Op, unsigned Imm, const APInt &Demanded,
     // Otherwise, create a machine node so that target independent DAG combine
     // doesn't undo this optimization.
   } else {
-    // Temporarily disable this optimization to avoid crashes
-    return false;
+    // bic/orn/eon
+    if (isLegalLogicalImmediate(NewImm, Subtarget)) {
+      SDValue EncConst = TLO.DAG.getTargetConstant(NewImm, DL, VT);
+      New = SDValue(
+          TLO.DAG.getMachineNode(NewOpc, DL, VT, Op.getOperand(0), EncConst),
+          0);
+    } else if ((Op.getOpcode() == ISD::AND ||
+                (Subtarget->isThumb2() && Op.getOpcode() == ISD::OR)) &&
+               isLegalLogicalImmediate(~NewImm, Subtarget)) {
+
+      if (Op.getOpcode() == ISD::OR) {
+        // ORN
+        NewOpc = ARM::t2ORNri;
+      } else {
+        // AND -> BIC
+        NewOpc = Subtarget->isThumb()
+                     ? Subtarget->isThumb2() ? ARM::t2BICri : ARM::tBIC
+                     : ARM::BICri;
+      }
+      SDValue EncConst = TLO.DAG.getTargetConstant(~NewImm, DL, VT);
+      New = SDValue(
+          TLO.DAG.getMachineNode(NewOpc, DL, VT, Op.getOperand(0), EncConst),
+          0);
+    } else {
+      return false;
+    }
   }
 
   return TLO.CombineTo(Op, New);