Use setCondCodeAction and getCondCodeAction

Author: wzssyqa

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -8424,6 +8424,12 @@ TargetLowering::createSelectForFMINNUM_FMAXNUM(SDNode *Node,
 
   if (Node->getFlags().hasNoNaNs()) {
     ISD::CondCode Pred = Opcode == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT;
+    EVT VT = Node->getValueType(0);
+    if ((!isCondCodeLegal(Pred, VT.getSimpleVT()) ||
+         !isOperationLegalOrCustom(ISD::VSELECT, VT)) &&
+        VT.isVector() &&
+        isOperationLegal(Node->getOpcode(), VT.getScalarType()))
+      return SDValue();
     SDValue Op1 = Node->getOperand(0);
     SDValue Op2 = Node->getOperand(1);
     SDValue SelCC = DAG.getSelectCC(SDLoc(Node), Op1, Op2, Op1, Op2, Pred);
@@ -8485,11 +8491,6 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode *Node,
                          Node->getOperand(1), Node->getFlags());
   }
 
-  // If we have INSN fitting this operation strictly for the elements of the
-  // vector, normally, splitting it is better than compare+select.
-  if (VT.isVector() && isOperationLegal(Node->getOpcode(), VT.getScalarType()))
-    return SDValue();
-
   if (SDValue SelCC = createSelectForFMINNUM_FMAXNUM(Node, DAG))
     return SelCC;
 

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -894,6 +894,10 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
     setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
     setOperationAction(ISD::FMA, MVT::v2f64, Expand);
+
+    for (auto CC : {ISD::SETOGT, ISD::SETOGE, ISD::SETOLT, ISD::SETOLE,
+                    ISD::SETGT, ISD::SETGE, ISD::SETLT, ISD::SETLE})
+      setCondCodeAction(CC, MVT::v2f64, Expand);
   }
 
   if (Subtarget->hasNEON()) {
@@ -915,6 +919,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
     setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
     setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
+    for (auto CC : {ISD::SETOGT, ISD::SETOGE, ISD::SETOLT, ISD::SETOLE,
+                    ISD::SETGT, ISD::SETGE, ISD::SETLT, ISD::SETLE})
+      setCondCodeAction(CC, MVT::v4f32, Expand);
 
     // Mark v2f32 intrinsics.
     setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
@@ -933,6 +940,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
     setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
     setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
+    for (auto CC : {ISD::SETOGT, ISD::SETOGE, ISD::SETOLT, ISD::SETOLE,
+                    ISD::SETGT, ISD::SETGE, ISD::SETLT, ISD::SETLE})
+      setCondCodeAction(CC, MVT::v2f32, Expand);
 
     // Neon does not support some operations on v1i64 and v2i64 types.
     setOperationAction(ISD::MUL, MVT::v1i64, Expand);