Address comments.

Author: kerbowa

llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h

@@ -163,7 +163,7 @@ struct AMDGPUFunctionArgInfo {
   // Map the index of preloaded kernel arguments to its descriptor.
   SmallDenseMap<int, KernArgPreloadDescriptor> PreloadKernArgs{};
   // The first user SGPR allocated for kernarg preloading.
-  Register FirstKernArgPreloadReg = AMDGPU::NoRegister;
+  Register FirstKernArgPreloadReg;
 
   std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
   getPreloadedValue(PreloadedValue Value) const;

llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.cpp

@@ -44,16 +44,7 @@ struct LoadConfig {
   unsigned Size;
   const TargetRegisterClass *RegClass;
   unsigned Opcode;
-  Register LoadReg;
-
-  // Constructor for the static config array
-  constexpr LoadConfig(unsigned S, const TargetRegisterClass *RC, unsigned Op)
-      : Size(S), RegClass(RC), Opcode(Op), LoadReg(AMDGPU::NoRegister) {}
-
-  // Constructor for the return value
-  constexpr LoadConfig(unsigned S, const TargetRegisterClass *RC, unsigned Op,
-                       Register Reg)
-      : Size(S), RegClass(RC), Opcode(Op), LoadReg(Reg) {}
+  Register LoadReg = Register();
 };
 
 class AMDGPUPreloadKernArgProlog {
@@ -162,7 +153,7 @@ void AMDGPUPreloadKernArgProlog::createBackCompatBlock(
   PadMBB->addSuccessor(&*KernelEntryMBB);
 }
 
-// Find the largest possible load size that fits with SGRP alignment
+/// Find the largest possible load size that fits with SGPR alignment
 static LoadConfig getLoadParameters(const TargetRegisterInfo &TRI,
                                     Register KernArgPreloadSGPR,
                                     unsigned NumKernArgPreloadSGPRs) {
@@ -175,14 +166,17 @@ static LoadConfig getLoadParameters(const TargetRegisterInfo &TRI,
     if (NumKernArgPreloadSGPRs >= Config.Size) {
       Register LoadReg = TRI.getMatchingSuperReg(KernArgPreloadSGPR,
                                                  AMDGPU::sub0, Config.RegClass);
-      if (LoadReg != AMDGPU::NoRegister)
-        return LoadConfig(Config.Size, Config.RegClass, Config.Opcode, LoadReg);
+      if (LoadReg) {
+        LoadConfig C(Config);
+        C.LoadReg = LoadReg;
+        return C;
+      }
     }
   }
 
   // Fallback to a single register
-  return LoadConfig(1, &AMDGPU::SReg_32RegClass, AMDGPU::S_LOAD_DWORD_IMM,
-                    KernArgPreloadSGPR);
+  return LoadConfig{1, &AMDGPU::SReg_32RegClass, AMDGPU::S_LOAD_DWORD_IMM,
+                    KernArgPreloadSGPR};
 }
 
 void AMDGPUPreloadKernArgProlog::addBackCompatLoads(

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

@@ -262,7 +262,7 @@ SmallVectorImpl<MCRegister> *SIMachineFunctionInfo::addPreloadedKernArg(
   // If the available register tuples are aligned with the kernarg to be
   // preloaded use that register, otherwise we need to use a set of SGPRs and
   // merge them.
-  if (ArgInfo.FirstKernArgPreloadReg == AMDGPU::NoRegister)
+  if (!ArgInfo.FirstKernArgPreloadReg)
     ArgInfo.FirstKernArgPreloadReg = getNextUserSGPR();
   Register PreloadReg =
       TRI.getMatchingSuperReg(getNextUserSGPR(), AMDGPU::sub0, RC);