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1 | 1 | // RUN: mlir-opt --test-gpu-rewrite -split-input-file %s | FileCheck %s |
2 | 2 |
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3 | | -module { |
4 | | - // CHECK-LABEL: func.func @subgroupId |
5 | | - // CHECK-SAME: (%[[SZ:.*]]: index, %[[MEM:.*]]: memref<index, 1>) { |
6 | | - func.func @subgroupId(%sz : index, %mem: memref<index, 1>) { |
7 | | - gpu.launch blocks(%bx, %by, %bz) in (%grid_x = %sz, %grid_y = %sz, %grid_z = %sz) |
8 | | - threads(%tx, %ty, %tz) in (%block_x = %sz, %block_y = %sz, %block_z = %sz) { |
9 | | - // CHECK: %[[DIMX:.*]] = gpu.block_dim x |
10 | | - // CHECK-NEXT: %[[DIMY:.*]] = gpu.block_dim y |
11 | | - // CHECK-NEXT: %[[TIDX:.*]] = gpu.thread_id x |
12 | | - // CHECK-NEXT: %[[TIDY:.*]] = gpu.thread_id y |
13 | | - // CHECK-NEXT: %[[TIDZ:.*]] = gpu.thread_id z |
14 | | - // CHECK-NEXT: %[[T0:.*]] = index.mul %[[DIMY]], %[[TIDZ]] |
15 | | - // CHECK-NEXT: %[[T1:.*]] = index.add %[[T0]], %[[TIDY]] |
16 | | - // CHECK-NEXT: %[[T2:.*]] = index.mul %[[DIMX]], %[[T1]] |
17 | | - // CHECK-NEXT: %[[T3:.*]] = index.add %[[TIDX]], %[[T2]] |
18 | | - // CHECK-NEXT: %[[T4:.*]] = gpu.subgroup_size : index |
19 | | - // CHECK-NEXT: %[[T5:.*]] = index.divu %[[T3]], %[[T4]] |
20 | | - %idz = gpu.subgroup_id : index |
21 | | - memref.store %idz, %mem[] : memref<index, 1> |
22 | | - gpu.terminator |
23 | | - } |
24 | | - return |
| 3 | +// CHECK-LABEL: func.func @subgroupId |
| 4 | +// CHECK-SAME: (%[[SZ:.*]]: index, %[[MEM:.*]]: memref<index, 1>) { |
| 5 | +func.func @subgroupId(%sz : index, %mem: memref<index, 1>) { |
| 6 | + gpu.launch blocks(%bx, %by, %bz) in (%grid_x = %sz, %grid_y = %sz, %grid_z = %sz) |
| 7 | + threads(%tx, %ty, %tz) in (%block_x = %sz, %block_y = %sz, %block_z = %sz) { |
| 8 | + // CHECK: %[[DIMX:.*]] = gpu.block_dim x |
| 9 | + // CHECK-NEXT: %[[DIMY:.*]] = gpu.block_dim y |
| 10 | + // CHECK-NEXT: %[[TIDX:.*]] = gpu.thread_id x |
| 11 | + // CHECK-NEXT: %[[TIDY:.*]] = gpu.thread_id y |
| 12 | + // CHECK-NEXT: %[[TIDZ:.*]] = gpu.thread_id z |
| 13 | + // CHECK-NEXT: %[[T0:.*]] = index.mul %[[DIMY]], %[[TIDZ]] |
| 14 | + // CHECK-NEXT: %[[T1:.*]] = index.add %[[T0]], %[[TIDY]] |
| 15 | + // CHECK-NEXT: %[[T2:.*]] = index.mul %[[DIMX]], %[[T1]] |
| 16 | + // CHECK-NEXT: %[[T3:.*]] = index.add %[[TIDX]], %[[T2]] |
| 17 | + // CHECK-NEXT: %[[T4:.*]] = gpu.subgroup_size : index |
| 18 | + // CHECK-NEXT: %[[T5:.*]] = index.divu %[[T3]], %[[T4]] |
| 19 | + %idz = gpu.subgroup_id : index |
| 20 | + memref.store %idz, %mem[] : memref<index, 1> |
| 21 | + gpu.terminator |
25 | 22 | } |
| 23 | + return |
26 | 24 | } |
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