Minor copilot comments

Author: justinrosner

mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td

@@ -1257,8 +1257,8 @@ def AMDGPU_ScaledWMMAOp
     per-block scaling of inputs, supporting fp4, fp6, and fp8 data formats.
 
     The scale instructions support a block size of 16 or 32 and two tile sizes:
-    - 16x16x128 with mixed f8/f6/f4 formats (output: vector<4xf32>)
-    - 32x16x128 with f4 format only (output: vector<8xf32>)
+    - 16x16x128 with mixed f8/f6/f4 formats (output: vector<8xf32>)
+    - 32x16x128 with f4 format only (output: vector<16xf32>)
 
     Scale parameters (`scaleA`, `scaleB`) are small vectors of f8 scale values
     (either f8E8M0FNU, or f8E4M3FN) that are packed into i32/i64 values during

mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp

@@ -485,7 +485,7 @@ LogicalResult ScaledWMMAOp::verify() {
              << bLen;
   } else { // m == 32
     // For 32×16×128: only fp4 is supported, A is 128, B is 64.
-    if (!isF4(aElemType))
+    if (!isF4(aElemType) && !isF4(bElemType))
       return emitOpError("32x16x128 only supports fp4 element types");
 
     if (aLen != 128)
@@ -513,12 +513,12 @@ LogicalResult ScaledWMMAOp::verify() {
   if (isE8M0(scaleAElemType) && isE8M0(scaleBElemType))
     return success();
 
-  // Matrix A (F8|F6) x Matrix B (F4) with Scale A (E8M0), Scale B (E5M2|E4M3).
+  // Matrix A (F8|F6) x Matrix B (F4) with Scale A (E8M0), Scale B (E5M3|E4M3).
   if ((isF8(aElemType) || isF6(aElemType)) && isE8M0(scaleAElemType) &&
       isF4(bElemType) && isE4M3(scaleBElemType))
     return success();
 
-  // Matrix A (F4) x Matrix B (F8|F6) with Scale A (E5M2|E4M3), Scale B (E8M0).
+  // Matrix A (F4) x Matrix B (F8|F6) with Scale A (E5M3|E4M3), Scale B (E8M0).
   if (isF4(aElemType) && isE4M3(scaleAElemType) &&
       (isF8(bElemType) || isF6(bElemType)) && isE8M0(scaleBElemType))
     return success();