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[RISCV] Add Qualcomm uC Xqcilb (Long Branch) extension
This extension adds two long branch instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0 This patch adds assembler only support. Change-Id: I262d59edc8c7266800badc82d6496619ce2aeabf
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -202,6 +202,7 @@
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// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension)
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// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
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// CHECK-NEXT: xqciint 0.4 'Xqciint' (Qualcomm uC Interrupts Extension)
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// CHECK-NEXT: xqcilb 0.2 'Xqcilb' (Qualcomm uC Long Branch Extension)
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// CHECK-NEXT: xqcili 0.2 'Xqcili' (Qualcomm uC Load Large Immediate Extension)
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// CHECK-NEXT: xqcilia 0.2 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
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// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)

‎llvm/docs/RISCVUsage.rst‎

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@@ -456,6 +456,9 @@ The current vendor extensions supported are:
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``experimental-Xqciint``
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LLVM implements `version 0.4 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcilb``
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LLVM implements `version 0.2 of the Qualcomm uC Long Branch extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcili``
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LLVM implements `version 0.2 of the Qualcomm uC Load Large Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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‎llvm/docs/ReleaseNotes.md‎

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@@ -110,6 +110,8 @@ Changes to the PowerPC Backend
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Changes to the RISC-V Backend
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-----------------------------
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* Adds experimental assembler support for the Qualcomm uC 'Xqcilb` (Long Branch)
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcili` (Load Large Immediate)
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large Immediate Arithmetic)

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

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@@ -1106,6 +1106,17 @@ struct RISCVOperand final : public MCParsedAsmOperand {
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VK == RISCVMCExpr::VK_RISCV_None;
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}
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bool isSImm32Lsb0() const {
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if (!isImm())
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return false;
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RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
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int64_t Imm;
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bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
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return IsConstantImm &&
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isShiftedInt<31, 1>(fixImmediateForRV32(Imm, isRV64Imm())) &&
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VK == RISCVMCExpr::VK_RISCV_None;
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}
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/// getStartLoc - Gets location of the first token of this operand
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SMLoc getStartLoc() const override { return StartLoc; }
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/// getEndLoc - Gets location of the last token of this operand
@@ -1729,6 +1740,11 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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return generateImmOutOfRangeError(Operands, ErrorInfo,
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std::numeric_limits<int32_t>::min(),
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std::numeric_limits<uint32_t>::max());
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case Match_InvalidSImm32Lsb0:
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return generateImmOutOfRangeError(
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Operands, ErrorInfo, std::numeric_limits<int32_t>::min(),
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std::numeric_limits<int32_t>::max() - 1,
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"operand must be a multiple of 2 bytes in the range ");
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case Match_InvalidRnumArg: {
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return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10);
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}

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

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@@ -651,9 +651,9 @@ static constexpr FeatureBitset XqciFeatureGroup = {
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RISCV::FeatureVendorXqcibm, RISCV::FeatureVendorXqcicli,
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RISCV::FeatureVendorXqcicm, RISCV::FeatureVendorXqcics,
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RISCV::FeatureVendorXqcicsr, RISCV::FeatureVendorXqciint,
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RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilia,
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RISCV::FeatureVendorXqcilo, RISCV::FeatureVendorXqcilsm,
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RISCV::FeatureVendorXqcisls,
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RISCV::FeatureVendorXqcili, RISCV::FeatureVendorXqcilb,
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RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
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RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisls,
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};
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static constexpr FeatureBitset XSfVectorGroup = {

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -1359,6 +1359,14 @@ def HasVendorXqciint
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AssemblerPredicate<(all_of FeatureVendorXqciint),
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"'Xqciint' (Qualcomm uC Interrupts Extension)">;
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def FeatureVendorXqcilb
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: RISCVExperimentalExtension<0, 2, "Qualcomm uC Long Branch Extension",
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[FeatureStdExtZca]>;
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def HasVendorXqcilb : Predicate<"Subtarget->hasVendorXqcilb()">,
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AssemblerPredicate<(all_of FeatureVendorXqcilb),
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"'Xqcilb' (Qualcomm uC oad Large Immediate Extension)">;
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def FeatureVendorXqcili
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: RISCVExperimentalExtension<0, 2, "Qualcomm uC Load Large Immediate Extension",
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[FeatureStdExtZca]>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

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@@ -75,6 +75,21 @@ def simm32 : RISCVOp<XLenVT> {
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}];
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}
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// A 32-bit signed immediate where the least significant bit is zero.
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def simm32_lsb0 : Operand<OtherVT> {
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let ParserMatchClass = SImmAsmOperand<32, "Lsb0">;
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let PrintMethod = "printBranchOperand";
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let EncoderMethod = "getImmOpValueAsr1";
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let DecoderMethod = "decodeSImmOperandAndLsl1<32>";
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let MCOperandPredicate = [{
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int64_t Imm;
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if (!MCOp.evaluateAsConstantImm(Imm))
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return false;
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return isShiftedInt<31, 1>(Imm);
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}];
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let OperandType = "OPERAND_PCREL";
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}
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//===----------------------------------------------------------------------===//
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// Instruction Formats
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//===----------------------------------------------------------------------===//
@@ -345,6 +360,24 @@ class QCIRVInstEI<bits<3> funct3, bits<2> funct2, string opcodestr>
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(ins GPRNoX0:$rs1, simm26:$imm), opcodestr,
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"$rd, $rs1, $imm">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class QCIRVInst48EJ<bits<2> func2, string opcodestr>
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: RVInst48<(outs), (ins simm32_lsb0:$imm31),
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opcodestr, "$imm31", [], InstFormatQCEJ> {
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bits<31> imm31;
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let Inst{47-32} = imm31{30-15};
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let Inst{31} = imm31{11};
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let Inst{30-25} = imm31{9-4};
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let Inst{24-20} = 0b00000;
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let Inst{19-17} = imm31{14-12};
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let Inst{16-15} = func2;
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let Inst{14-12} = 0b100;
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let Inst{11-8} = imm31{3-0};
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let Inst{7} = imm31{10};
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let Inst{6-0} = 0b0011111;
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}
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348381
//===----------------------------------------------------------------------===//
349382
// Instructions
350383
//===----------------------------------------------------------------------===//
@@ -593,6 +626,13 @@ let Predicates = [HasVendorXqcilo, IsRV32] in {
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def QC_E_SW : QCIRVInstESStore<0b110, 0b11, "qc.e.sw">;
594627
} // Predicates = [HasVendorXqcilo, IsRV32]
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let Predicates = [HasVendorXqcilb, IsRV32] in {
630+
let isCall = 1, Defs = [X1] in
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def QC_E_JAL : QCIRVInst48EJ<0b01, "qc.e.jal">;
632+
let isBranch = 1, isTerminator = 1, isBarrier = 1 in
633+
def QC_E_J : QCIRVInst48EJ<0b00, "qc.e.j">;
634+
} // Predicates = [HasVendorXqcilb, IsRV32]
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let Predicates = [HasVendorXqcili, IsRV32] in {
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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def QC_LI : RVInstU<OPC_OP_IMM_32, (outs GPRNoX0:$rd), (ins simm20:$imm20),

‎llvm/lib/TargetParser/RISCVISAInfo.cpp‎

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@@ -744,9 +744,9 @@ Error RISCVISAInfo::checkDependency() {
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bool HasXqccmp = Exts.count("xqccmp") != 0;
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static constexpr StringLiteral XqciExts[] = {
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{"xqcia"}, {"xqciac"}, {"xqcibm"}, {"xqcicli"}, {"xqcicm"},
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{"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcili"}, {"xqcilia"},
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{"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
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{"xqcia"}, {"xqciac"}, {"xqcibm"}, {"xqcicli"}, {"xqcicm"},
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{"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcilb"}, {"xqcili"},
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{"xqcilia"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
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static constexpr StringLiteral ZcdOverlaps[] = {
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{"zcmt"}, {"zcmp"}, {"xqccmp"}, {"xqciac"}, {"xqcicm"}};
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‎llvm/test/CodeGen/RISCV/attributes.ll‎

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@@ -90,6 +90,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciint %s -o - | FileCheck --check-prefix=RV32XQCIINT %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilb %s -o - | FileCheck --check-prefix=RV32XQCILB %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcili %s -o - | FileCheck --check-prefix=RV32XQCILI %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilia %s -o - | FileCheck --check-prefix=RV32XQCILIA %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo %s -o - | FileCheck --check-prefix=RV32XQCILO %s
@@ -413,6 +414,7 @@
413414
; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2"
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; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
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; RV32XQCIINT: .attribute 5, "rv32i2p1_zca1p0_xqciint0p4"
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; RV32XQCILB: .attribute 5, "rv32i2p1_zca1p0_xqcilb0p2"
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; RV32XQCILI: .attribute 5, "rv32i2p1_zca1p0_xqcili0p2"
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; RV32XQCILIA: .attribute 5, "rv32i2p1_zca1p0_xqcilia0p2"
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; RV32XQCILO: .attribute 5, "rv32i2p1_zca1p0_xqcilo0p2"

‎llvm/test/MC/RISCV/xqcilb-invalid.s‎

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@@ -0,0 +1,24 @@
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# Xqcilb - Qualcomm uC Long Branch Extension
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcilb < %s 2>&1 \
3+
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s
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# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcilb < %s 2>&1 \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
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7+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.e.j
9+
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# CHECK-PLUS: :[[@LINE+1]]:9: error: operand must be a multiple of 2 bytes in the range [-2147483648, 2147483646]
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qc.e.j -2147483649
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilb' (Qualcomm uC Long Branch Extension)
14+
qc.e.j -2147483648
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16+
17+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
18+
qc.e.jal
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# CHECK-PLUS: :[[@LINE+1]]:10: error: operand must be a multiple of 2 bytes in the range [-2147483648, 2147483646]
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qc.e.jal 2147483649
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23+
# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilb' (Qualcomm uC Long Branch Extension)
24+
qc.e.jal 2147483640

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