rebase

Created using spr 1.3.5-bogner

Author: MaskRay

llvm/include/llvm/MC/MCFixup.h

@@ -34,10 +34,6 @@ enum MCFixupKind : uint16_t {
   FK_Data_4,      ///< A four-byte fixup.
   FK_Data_8,      ///< A eight-byte fixup.
   FK_Data_leb128, ///< A leb128 fixup.
-  FK_PCRel_1,     ///< A one-byte pc relative fixup.
-  FK_PCRel_2,     ///< A two-byte pc relative fixup.
-  FK_PCRel_4,     ///< A four-byte pc relative fixup.
-  FK_PCRel_8,     ///< A eight-byte pc relative fixup.
   FK_SecRel_1,    ///< A one-byte section relative fixup.
   FK_SecRel_2,    ///< A two-byte section relative fixup.
   FK_SecRel_4,    ///< A four-byte section relative fixup.

llvm/lib/MC/MCAsmBackend.cpp

@@ -95,10 +95,6 @@ MCFixupKindInfo MCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
       {"FK_Data_4", 0, 32, 0},
       {"FK_Data_8", 0, 64, 0},
       {"FK_Data_leb128", 0, 0, 0},
-      {"FK_PCRel_1", 0, 8, 0},
-      {"FK_PCRel_2", 0, 16, 0},
-      {"FK_PCRel_4", 0, 32, 0},
-      {"FK_PCRel_8", 0, 64, 0},
       {"FK_SecRel_1", 0, 8, 0},
       {"FK_SecRel_2", 0, 16, 0},
       {"FK_SecRel_4", 0, 32, 0},

llvm/lib/MC/MCAsmStreamer.cpp

@@ -2414,9 +2414,14 @@ void MCAsmStreamer::AddEncodingComment(const MCInst &Inst,
     auto Kind = F.getKind();
     if (mc::isRelocation(Kind))
       OS << ", relocation type: " << Kind;
-    else
-      OS << ", kind: "
-         << getAssembler().getBackend().getFixupKindInfo(Kind).Name;
+    else {
+      OS << ", kind: ";
+      auto Info = getAssembler().getBackend().getFixupKindInfo(Kind);
+      if (F.isPCRel() && StringRef(Info.Name).starts_with("FK_Data_"))
+        OS << "FK_PCRel_" << (Info.TargetSize / 8);
+      else
+        OS << Info.Name;
+    }
     OS << '\n';
   }
 }

llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp

@@ -49,16 +49,18 @@ unsigned AArch64WinCOFFObjectWriter::getRelocType(
     MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup,
     bool IsCrossSection, const MCAsmBackend &MAB) const {
   unsigned FixupKind = Fixup.getKind();
+  bool PCRel = Fixup.isPCRel();
   if (IsCrossSection) {
     // IMAGE_REL_ARM64_REL64 does not exist. We treat FK_Data_8 as FK_PCRel_4 so
     // that .xword a-b can lower to IMAGE_REL_ARM64_REL32. This allows generic
     // instrumentation to not bother with the COFF limitation. A negative value
     // needs attention.
-    if (FixupKind != FK_Data_4 && FixupKind != FK_Data_8) {
+    if (PCRel || (FixupKind != FK_Data_4 && FixupKind != FK_Data_8)) {
       Ctx.reportError(Fixup.getLoc(), "Cannot represent this expression");
       return COFF::IMAGE_REL_ARM64_ADDR32;
     }
-    FixupKind = FK_PCRel_4;
+    FixupKind = FK_Data_4;
+    PCRel = true;
   }
 
   auto Spec = Target.getSpecifier();
@@ -93,10 +95,9 @@ unsigned AArch64WinCOFFObjectWriter::getRelocType(
     return COFF::IMAGE_REL_ARM64_ABSOLUTE; // Dummy return value
   }
 
-  case FK_PCRel_4:
-    return COFF::IMAGE_REL_ARM64_REL32;
-
   case FK_Data_4:
+    if (PCRel)
+      return COFF::IMAGE_REL_ARM64_REL32;
     switch (Spec) {
     default:
       return COFF::IMAGE_REL_ARM64_ADDR32;

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

@@ -94,7 +94,6 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
     return 2;
   case FK_SecRel_4:
   case FK_Data_4:
-  case FK_PCRel_4:
     return 4;
   case FK_SecRel_8:
   case FK_Data_8:
@@ -121,7 +120,6 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
   case FK_Data_2:
   case FK_Data_4:
   case FK_Data_8:
-  case FK_PCRel_4:
   case FK_SecRel_4:
     return Value;
   default:

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp

@@ -69,8 +69,6 @@ unsigned AMDGPUELFObjectWriter::getRelocType(const MCFixup &Fixup,
   MCFixupKind Kind = Fixup.getKind();
   switch (Kind) {
   default: break;
-  case FK_PCRel_4:
-    return ELF::R_AMDGPU_REL32;
   case FK_Data_4:
   case FK_SecRel_4:
     return IsPCRel ? ELF::R_AMDGPU_REL32 : ELF::R_AMDGPU_ABS32;

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp

@@ -656,16 +656,11 @@ void AMDGPUMCCodeEmitter::getMachineOpValueCommon(
     //
     // .Ltmp1:
     //   s_add_u32 s2, s2, (extern_const_addrspace+16)-.Ltmp1
-    MCFixupKind Kind;
-    if (needsPCRel(MO.getExpr()))
-      Kind = FK_PCRel_4;
-    else
-      Kind = FK_Data_4;
-
+    bool PCRel = needsPCRel(MO.getExpr());
     const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
     uint32_t Offset = Desc.getSize();
     assert(Offset == 4 || Offset == 8);
-    addFixup(Fixups, Offset, MO.getExpr(), Kind, Kind == FK_PCRel_4);
+    addFixup(Fixups, Offset, MO.getExpr(), FK_Data_4, PCRel);
   }
 
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());

llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp

@@ -47,12 +47,14 @@ unsigned ARMWinCOFFObjectWriter::getRelocType(MCContext &Ctx,
                                               const MCAsmBackend &MAB) const {
   auto Spec = Target.getSpecifier();
   unsigned FixupKind = Fixup.getKind();
+  bool PCRel = false;
   if (IsCrossSection) {
-    if (FixupKind != FK_Data_4) {
+    if (PCRel || FixupKind != FK_Data_4) {
       Ctx.reportError(Fixup.getLoc(), "Cannot represent this expression");
       return COFF::IMAGE_REL_ARM_ADDR32;
     }
-    FixupKind = FK_PCRel_4;
+    FixupKind = FK_Data_4;
+    PCRel = true;
   }
 
 
@@ -62,6 +64,8 @@ unsigned ARMWinCOFFObjectWriter::getRelocType(MCContext &Ctx,
     return COFF::IMAGE_REL_ARM_ABSOLUTE;
   }
   case FK_Data_4:
+    if (PCRel)
+      return COFF::IMAGE_REL_ARM_REL32;
     switch (Spec) {
     case MCSymbolRefExpr::VK_COFF_IMGREL32:
       return COFF::IMAGE_REL_ARM_ADDR32NB;
@@ -70,8 +74,6 @@ unsigned ARMWinCOFFObjectWriter::getRelocType(MCContext &Ctx,
     default:
       return COFF::IMAGE_REL_ARM_ADDR32;
     }
-  case FK_PCRel_4:
-    return COFF::IMAGE_REL_ARM_REL32;
   case FK_SecRel_2:
     return COFF::IMAGE_REL_ARM_SECTION;
   case FK_SecRel_4:

llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp

@@ -78,11 +78,11 @@ void BPFAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
     support::endian::write<uint32_t>(&Data[Fixup.getOffset() + 4],
                                      static_cast<uint32_t>(Value),
                                      Endian);
-  } else if (Fixup.getKind() == FK_Data_4) {
+  } else if (Fixup.getKind() == FK_Data_4 && !Fixup.isPCRel()) {
     support::endian::write<uint32_t>(&Data[Fixup.getOffset()], Value, Endian);
   } else if (Fixup.getKind() == FK_Data_8) {
     support::endian::write<uint64_t>(&Data[Fixup.getOffset()], Value, Endian);
-  } else if (Fixup.getKind() == FK_PCRel_4) {
+  } else if (Fixup.getKind() == FK_Data_4 && Fixup.isPCRel()) {
     Value = (uint32_t)((Value - 8) / 8);
     if (Endian == llvm::endianness::little) {
       Data[Fixup.getOffset() + 1] = 0x10;
@@ -97,7 +97,7 @@ void BPFAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
     support::endian::write<uint32_t>(&Data[Fixup.getOffset() + 4], Value,
                                      Endian);
   } else {
-    assert(Fixup.getKind() == FK_PCRel_2);
+    assert(Fixup.getKind() == FK_Data_2 && Fixup.isPCRel());
 
     int64_t ByteOff = (int64_t)Value - 8;
     if (ByteOff > INT16_MAX * 8 || ByteOff < INT16_MIN * 8)

llvm/lib/Target/BPF/MCTargetDesc/BPFELFObjectWriter.cpp

@@ -45,12 +45,11 @@ unsigned BPFELFObjectWriter::getRelocType(const MCFixup &Fixup,
   case FK_SecRel_8:
     // LD_imm64 instruction.
     return ELF::R_BPF_64_64;
-  case FK_PCRel_4:
-    // CALL instruction.
-    return ELF::R_BPF_64_32;
   case FK_Data_8:
     return ELF::R_BPF_64_ABS64;
   case FK_Data_4:
+    if (Fixup.isPCRel()) // CALL instruction
+      return ELF::R_BPF_64_32;
     if (const auto *A = Target.getAddSym()) {
       const MCSymbol &Sym = *A;