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artagnonartagnon
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[VPlan] Simplify x && false -> false, x | 0 -> x (#156345)
The OR x, 0 -> x simplification has been introduced to avoid regressions.
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4 files changed

+68
-131
lines changed

4 files changed

+68
-131
lines changed

‎llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp‎

Lines changed: 14 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1081,20 +1081,21 @@ static void simplifyRecipe(VPRecipeBase &R, VPTypeAnalysis &TypeInfo) {
10811081
return;
10821082
}
10831083

1084-
// OR x, 1 -> 1.
1085-
if (match(Def, m_c_BinaryOr(m_VPValue(X), m_AllOnes()))) {
1086-
Def->replaceAllUsesWith(Def->getOperand(0) == X ? Def->getOperand(1)
1087-
: Def->getOperand(0));
1088-
Def->eraseFromParent();
1089-
return;
1090-
}
1084+
// x | 1 -> 1
1085+
if (match(Def, m_c_BinaryOr(m_VPValue(X), m_AllOnes())))
1086+
return Def->replaceAllUsesWith(Def->getOperand(Def->getOperand(0) == X));
10911087

1092-
// AND x, 0 -> 0
1093-
if (match(&R, m_c_BinaryAnd(m_VPValue(X), m_ZeroInt()))) {
1094-
Def->replaceAllUsesWith(R.getOperand(0) == X ? R.getOperand(1)
1095-
: R.getOperand(0));
1096-
return;
1097-
}
1088+
// x | 0 -> x
1089+
if (match(Def, m_c_BinaryOr(m_VPValue(X), m_ZeroInt())))
1090+
return Def->replaceAllUsesWith(X);
1091+
1092+
// x & 0 -> 0
1093+
if (match(Def, m_c_BinaryAnd(m_VPValue(X), m_ZeroInt())))
1094+
return Def->replaceAllUsesWith(Def->getOperand(Def->getOperand(0) == X));
1095+
1096+
// x && false -> false
1097+
if (match(Def, m_LogicalAnd(m_VPValue(X), m_False())))
1098+
return Def->replaceAllUsesWith(Def->getOperand(1));
10981099

10991100
// (x && y) || (x && z) -> x && (y || z)
11001101
VPBuilder Builder(Def);

‎llvm/test/Transforms/LoopVectorize/AArch64/blend-costs.ll‎

Lines changed: 49 additions & 71 deletions
Original file line numberDiff line numberDiff line change
@@ -16,128 +16,106 @@ define void @test_blend_feeding_replicated_store_1(i64 %N, ptr noalias %src, ptr
1616
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
1717
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i64 16, i64 [[N_MOD_VF]]
1818
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP43]], [[TMP2]]
19-
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x ptr> poison, ptr [[DST]], i64 0
20-
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x ptr> [[BROADCAST_SPLATINSERT]], <16 x ptr> poison, <16 x i32> zeroinitializer
2119
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
2220
; CHECK: [[VECTOR_BODY]]:
2321
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE30:.*]] ]
2422
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]
2523
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i32>, ptr [[TMP4]], align 4
26-
; CHECK-NEXT: [[TMP6:%.*]] = icmp slt <16 x i32> [[WIDE_LOAD]], zeroinitializer
27-
; CHECK-NEXT: [[TMP7:%.*]] = select <16 x i1> [[TMP6]], <16 x i1> zeroinitializer, <16 x i1> zeroinitializer
28-
; CHECK-NEXT: [[TMP8:%.*]] = xor <16 x i1> [[TMP6]], splat (i1 true)
29-
; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i1> [[TMP7]], [[TMP8]]
30-
; CHECK-NEXT: [[PREDPHI:%.*]] = select <16 x i1> [[TMP6]], <16 x ptr> [[BROADCAST_SPLAT]], <16 x ptr> zeroinitializer
31-
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <16 x i1> [[TMP9]], i32 0
32-
; CHECK-NEXT: br i1 [[TMP10]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
24+
; CHECK-NEXT: [[TMP5:%.*]] = icmp sge <16 x i32> [[WIDE_LOAD]], zeroinitializer
25+
; CHECK-NEXT: [[TMP21:%.*]] = extractelement <16 x i1> [[TMP5]], i32 0
26+
; CHECK-NEXT: br i1 [[TMP21]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
3327
; CHECK: [[PRED_STORE_IF]]:
34-
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 0
35-
; CHECK-NEXT: store i8 0, ptr [[TMP11]], align 1
28+
; CHECK-NEXT: store i8 0, ptr null, align 1
3629
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]
3730
; CHECK: [[PRED_STORE_CONTINUE]]:
38-
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <16 x i1> [[TMP9]], i32 1
39-
; CHECK-NEXT: br i1 [[TMP12]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]
31+
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <16 x i1> [[TMP5]], i32 1
32+
; CHECK-NEXT: br i1 [[TMP6]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]
4033
; CHECK: [[PRED_STORE_IF1]]:
41-
; CHECK-NEXT: [[TMP13:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 1
42-
; CHECK-NEXT: store i8 0, ptr [[TMP13]], align 1
34+
; CHECK-NEXT: store i8 0, ptr null, align 1
4335
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE2]]
4436
; CHECK: [[PRED_STORE_CONTINUE2]]:
45-
; CHECK-NEXT: [[TMP14:%.*]] = extractelement <16 x i1> [[TMP9]], i32 2
46-
; CHECK-NEXT: br i1 [[TMP14]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]
37+
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <16 x i1> [[TMP5]], i32 2
38+
; CHECK-NEXT: br i1 [[TMP7]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]
4739
; CHECK: [[PRED_STORE_IF3]]:
48-
; CHECK-NEXT: [[TMP15:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 2
49-
; CHECK-NEXT: store i8 0, ptr [[TMP15]], align 1
40+
; CHECK-NEXT: store i8 0, ptr null, align 1
5041
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]
5142
; CHECK: [[PRED_STORE_CONTINUE4]]:
52-
; CHECK-NEXT: [[TMP16:%.*]] = extractelement <16 x i1> [[TMP9]], i32 3
53-
; CHECK-NEXT: br i1 [[TMP16]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]
43+
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <16 x i1> [[TMP5]], i32 3
44+
; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]
5445
; CHECK: [[PRED_STORE_IF5]]:
55-
; CHECK-NEXT: [[TMP17:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 3
56-
; CHECK-NEXT: store i8 0, ptr [[TMP17]], align 1
46+
; CHECK-NEXT: store i8 0, ptr null, align 1
5747
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]]
5848
; CHECK: [[PRED_STORE_CONTINUE6]]:
59-
; CHECK-NEXT: [[TMP18:%.*]] = extractelement <16 x i1> [[TMP9]], i32 4
60-
; CHECK-NEXT: br i1 [[TMP18]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]
49+
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <16 x i1> [[TMP5]], i32 4
50+
; CHECK-NEXT: br i1 [[TMP9]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]
6151
; CHECK: [[PRED_STORE_IF7]]:
62-
; CHECK-NEXT: [[TMP19:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 4
63-
; CHECK-NEXT: store i8 0, ptr [[TMP19]], align 1
52+
; CHECK-NEXT: store i8 0, ptr null, align 1
6453
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE8]]
6554
; CHECK: [[PRED_STORE_CONTINUE8]]:
66-
; CHECK-NEXT: [[TMP20:%.*]] = extractelement <16 x i1> [[TMP9]], i32 5
67-
; CHECK-NEXT: br i1 [[TMP20]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]]
55+
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <16 x i1> [[TMP5]], i32 5
56+
; CHECK-NEXT: br i1 [[TMP10]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]]
6857
; CHECK: [[PRED_STORE_IF9]]:
69-
; CHECK-NEXT: [[TMP21:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 5
70-
; CHECK-NEXT: store i8 0, ptr [[TMP21]], align 1
58+
; CHECK-NEXT: store i8 0, ptr null, align 1
7159
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE10]]
7260
; CHECK: [[PRED_STORE_CONTINUE10]]:
73-
; CHECK-NEXT: [[TMP22:%.*]] = extractelement <16 x i1> [[TMP9]], i32 6
74-
; CHECK-NEXT: br i1 [[TMP22]], label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12:.*]]
61+
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <16 x i1> [[TMP5]], i32 6
62+
; CHECK-NEXT: br i1 [[TMP11]], label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12:.*]]
7563
; CHECK: [[PRED_STORE_IF11]]:
76-
; CHECK-NEXT: [[TMP23:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 6
77-
; CHECK-NEXT: store i8 0, ptr [[TMP23]], align 1
64+
; CHECK-NEXT: store i8 0, ptr null, align 1
7865
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE12]]
7966
; CHECK: [[PRED_STORE_CONTINUE12]]:
80-
; CHECK-NEXT: [[TMP24:%.*]] = extractelement <16 x i1> [[TMP9]], i32 7
81-
; CHECK-NEXT: br i1 [[TMP24]], label %[[PRED_STORE_IF13:.*]], label %[[PRED_STORE_CONTINUE14:.*]]
67+
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <16 x i1> [[TMP5]], i32 7
68+
; CHECK-NEXT: br i1 [[TMP12]], label %[[PRED_STORE_IF13:.*]], label %[[PRED_STORE_CONTINUE14:.*]]
8269
; CHECK: [[PRED_STORE_IF13]]:
83-
; CHECK-NEXT: [[TMP25:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 7
84-
; CHECK-NEXT: store i8 0, ptr [[TMP25]], align 1
70+
; CHECK-NEXT: store i8 0, ptr null, align 1
8571
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE14]]
8672
; CHECK: [[PRED_STORE_CONTINUE14]]:
87-
; CHECK-NEXT: [[TMP26:%.*]] = extractelement <16 x i1> [[TMP9]], i32 8
88-
; CHECK-NEXT: br i1 [[TMP26]], label %[[PRED_STORE_IF15:.*]], label %[[PRED_STORE_CONTINUE16:.*]]
73+
; CHECK-NEXT: [[TMP13:%.*]] = extractelement <16 x i1> [[TMP5]], i32 8
74+
; CHECK-NEXT: br i1 [[TMP13]], label %[[PRED_STORE_IF15:.*]], label %[[PRED_STORE_CONTINUE16:.*]]
8975
; CHECK: [[PRED_STORE_IF15]]:
90-
; CHECK-NEXT: [[TMP27:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 8
91-
; CHECK-NEXT: store i8 0, ptr [[TMP27]], align 1
76+
; CHECK-NEXT: store i8 0, ptr null, align 1
9277
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE16]]
9378
; CHECK: [[PRED_STORE_CONTINUE16]]:
94-
; CHECK-NEXT: [[TMP28:%.*]] = extractelement <16 x i1> [[TMP9]], i32 9
95-
; CHECK-NEXT: br i1 [[TMP28]], label %[[PRED_STORE_IF17:.*]], label %[[PRED_STORE_CONTINUE18:.*]]
79+
; CHECK-NEXT: [[TMP14:%.*]] = extractelement <16 x i1> [[TMP5]], i32 9
80+
; CHECK-NEXT: br i1 [[TMP14]], label %[[PRED_STORE_IF17:.*]], label %[[PRED_STORE_CONTINUE18:.*]]
9681
; CHECK: [[PRED_STORE_IF17]]:
97-
; CHECK-NEXT: [[TMP29:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 9
98-
; CHECK-NEXT: store i8 0, ptr [[TMP29]], align 1
82+
; CHECK-NEXT: store i8 0, ptr null, align 1
9983
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE18]]
10084
; CHECK: [[PRED_STORE_CONTINUE18]]:
101-
; CHECK-NEXT: [[TMP30:%.*]] = extractelement <16 x i1> [[TMP9]], i32 10
102-
; CHECK-NEXT: br i1 [[TMP30]], label %[[PRED_STORE_IF19:.*]], label %[[PRED_STORE_CONTINUE20:.*]]
85+
; CHECK-NEXT: [[TMP15:%.*]] = extractelement <16 x i1> [[TMP5]], i32 10
86+
; CHECK-NEXT: br i1 [[TMP15]], label %[[PRED_STORE_IF19:.*]], label %[[PRED_STORE_CONTINUE20:.*]]
10387
; CHECK: [[PRED_STORE_IF19]]:
104-
; CHECK-NEXT: [[TMP31:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 10
105-
; CHECK-NEXT: store i8 0, ptr [[TMP31]], align 1
88+
; CHECK-NEXT: store i8 0, ptr null, align 1
10689
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE20]]
10790
; CHECK: [[PRED_STORE_CONTINUE20]]:
108-
; CHECK-NEXT: [[TMP32:%.*]] = extractelement <16 x i1> [[TMP9]], i32 11
109-
; CHECK-NEXT: br i1 [[TMP32]], label %[[PRED_STORE_IF21:.*]], label %[[PRED_STORE_CONTINUE22:.*]]
91+
; CHECK-NEXT: [[TMP16:%.*]] = extractelement <16 x i1> [[TMP5]], i32 11
92+
; CHECK-NEXT: br i1 [[TMP16]], label %[[PRED_STORE_IF21:.*]], label %[[PRED_STORE_CONTINUE22:.*]]
11093
; CHECK: [[PRED_STORE_IF21]]:
111-
; CHECK-NEXT: [[TMP33:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 11
112-
; CHECK-NEXT: store i8 0, ptr [[TMP33]], align 1
94+
; CHECK-NEXT: store i8 0, ptr null, align 1
11395
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE22]]
11496
; CHECK: [[PRED_STORE_CONTINUE22]]:
115-
; CHECK-NEXT: [[TMP34:%.*]] = extractelement <16 x i1> [[TMP9]], i32 12
116-
; CHECK-NEXT: br i1 [[TMP34]], label %[[PRED_STORE_IF23:.*]], label %[[PRED_STORE_CONTINUE24:.*]]
97+
; CHECK-NEXT: [[TMP17:%.*]] = extractelement <16 x i1> [[TMP5]], i32 12
98+
; CHECK-NEXT: br i1 [[TMP17]], label %[[PRED_STORE_IF23:.*]], label %[[PRED_STORE_CONTINUE24:.*]]
11799
; CHECK: [[PRED_STORE_IF23]]:
118-
; CHECK-NEXT: [[TMP35:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 12
119-
; CHECK-NEXT: store i8 0, ptr [[TMP35]], align 1
100+
; CHECK-NEXT: store i8 0, ptr null, align 1
120101
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE24]]
121102
; CHECK: [[PRED_STORE_CONTINUE24]]:
122-
; CHECK-NEXT: [[TMP36:%.*]] = extractelement <16 x i1> [[TMP9]], i32 13
123-
; CHECK-NEXT: br i1 [[TMP36]], label %[[PRED_STORE_IF25:.*]], label %[[PRED_STORE_CONTINUE26:.*]]
103+
; CHECK-NEXT: [[TMP18:%.*]] = extractelement <16 x i1> [[TMP5]], i32 13
104+
; CHECK-NEXT: br i1 [[TMP18]], label %[[PRED_STORE_IF25:.*]], label %[[PRED_STORE_CONTINUE26:.*]]
124105
; CHECK: [[PRED_STORE_IF25]]:
125-
; CHECK-NEXT: [[TMP37:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 13
126-
; CHECK-NEXT: store i8 0, ptr [[TMP37]], align 1
106+
; CHECK-NEXT: store i8 0, ptr null, align 1
127107
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE26]]
128108
; CHECK: [[PRED_STORE_CONTINUE26]]:
129-
; CHECK-NEXT: [[TMP38:%.*]] = extractelement <16 x i1> [[TMP9]], i32 14
130-
; CHECK-NEXT: br i1 [[TMP38]], label %[[PRED_STORE_IF27:.*]], label %[[PRED_STORE_CONTINUE28:.*]]
109+
; CHECK-NEXT: [[TMP19:%.*]] = extractelement <16 x i1> [[TMP5]], i32 14
110+
; CHECK-NEXT: br i1 [[TMP19]], label %[[PRED_STORE_IF27:.*]], label %[[PRED_STORE_CONTINUE28:.*]]
131111
; CHECK: [[PRED_STORE_IF27]]:
132-
; CHECK-NEXT: [[TMP39:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 14
133-
; CHECK-NEXT: store i8 0, ptr [[TMP39]], align 1
112+
; CHECK-NEXT: store i8 0, ptr null, align 1
134113
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE28]]
135114
; CHECK: [[PRED_STORE_CONTINUE28]]:
136-
; CHECK-NEXT: [[TMP40:%.*]] = extractelement <16 x i1> [[TMP9]], i32 15
137-
; CHECK-NEXT: br i1 [[TMP40]], label %[[PRED_STORE_IF29:.*]], label %[[PRED_STORE_CONTINUE30]]
115+
; CHECK-NEXT: [[TMP20:%.*]] = extractelement <16 x i1> [[TMP5]], i32 15
116+
; CHECK-NEXT: br i1 [[TMP20]], label %[[PRED_STORE_IF29:.*]], label %[[PRED_STORE_CONTINUE30]]
138117
; CHECK: [[PRED_STORE_IF29]]:
139-
; CHECK-NEXT: [[TMP41:%.*]] = extractelement <16 x ptr> [[PREDPHI]], i32 15
140-
; CHECK-NEXT: store i8 0, ptr [[TMP41]], align 1
118+
; CHECK-NEXT: store i8 0, ptr null, align 1
141119
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE30]]
142120
; CHECK: [[PRED_STORE_CONTINUE30]]:
143121
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16

‎llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,9 +31,8 @@ define void @type_info_cache_clobber(ptr %dstv, ptr %src, i64 %wide.trip.count)
3131
; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 8 x i8> @llvm.vp.load.nxv8i8.p0(ptr align 1 [[TMP13]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP11]]), !alias.scope [[META0:![0-9]+]]
3232
; CHECK-NEXT: [[TMP15:%.*]] = zext <vscale x 8 x i8> [[VP_OP_LOAD]] to <vscale x 8 x i32>
3333
; CHECK-NEXT: [[TMP23:%.*]] = ashr <vscale x 8 x i32> [[TMP15]], zeroinitializer
34-
; CHECK-NEXT: [[VP_OP3:%.*]] = or <vscale x 8 x i32> [[TMP23]], zeroinitializer
3534
; CHECK-NEXT: [[TMP16:%.*]] = icmp ult <vscale x 8 x i32> [[TMP15]], zeroinitializer
36-
; CHECK-NEXT: [[TMP17:%.*]] = select <vscale x 8 x i1> [[TMP16]], <vscale x 8 x i32> [[VP_OP3]], <vscale x 8 x i32> zeroinitializer
35+
; CHECK-NEXT: [[TMP17:%.*]] = select <vscale x 8 x i1> [[TMP16]], <vscale x 8 x i32> [[TMP23]], <vscale x 8 x i32> zeroinitializer
3736
; CHECK-NEXT: [[TMP24:%.*]] = trunc <vscale x 8 x i32> [[TMP17]] to <vscale x 8 x i8>
3837
; CHECK-NEXT: call void @llvm.vp.scatter.nxv8i8.nxv8p0(<vscale x 8 x i8> [[TMP24]], <vscale x 8 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP11]]), !alias.scope [[META3:![0-9]+]], !noalias [[META0]]
3938
; CHECK-NEXT: call void @llvm.vp.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x ptr> align 2 zeroinitializer, <vscale x 8 x i1> splat (i1 true), i32 [[TMP11]])

‎llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll‎

Lines changed: 4 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -341,64 +341,23 @@ exit:
341341
define void @redundant_and_2(ptr %dst, i1 %c.0, i1 %c.1) {
342342
; CHECK-LABEL: @redundant_and_2(
343343
; CHECK-NEXT: entry:
344-
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
345-
; CHECK: vector.ph:
346-
; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i1> poison, i1 [[C_0:%.*]], i64 0
347-
; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT1]], <4 x i1> poison, <4 x i32> zeroinitializer
348-
; CHECK-NEXT: [[TMP0:%.*]] = xor <4 x i1> [[BROADCAST_SPLAT2]], splat (i1 true)
349-
; CHECK-NEXT: [[TMP1:%.*]] = select <4 x i1> [[TMP0]], <4 x i1> zeroinitializer, <4 x i1> zeroinitializer
350-
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
351-
; CHECK: vector.body:
352-
; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i1> [[TMP1]], <4 x i1> zeroinitializer
353-
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP4]], i32 0
354-
; CHECK-NEXT: br i1 [[TMP5]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
355-
; CHECK: pred.store.if:
356-
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 0
357-
; CHECK-NEXT: store i32 0, ptr [[TMP7]], align 4
358-
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]]
359-
; CHECK: pred.store.continue:
360-
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP4]], i32 1
361-
; CHECK-NEXT: br i1 [[TMP8]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]]
362-
; CHECK: pred.store.if1:
363-
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 1
364-
; CHECK-NEXT: store i32 0, ptr [[TMP10]], align 4
365-
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]]
366-
; CHECK: pred.store.continue2:
367-
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP4]], i32 2
368-
; CHECK-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]]
369-
; CHECK: pred.store.if3:
370-
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 2
371-
; CHECK-NEXT: store i32 0, ptr [[TMP13]], align 4
372-
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]]
373-
; CHECK: pred.store.continue4:
374-
; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i1> [[TMP4]], i32 3
375-
; CHECK-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]]
376-
; CHECK: pred.store.if5:
377-
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 3
378-
; CHECK-NEXT: store i32 0, ptr [[TMP16]], align 4
379-
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE8]]
380-
; CHECK: pred.store.continue6:
381-
; CHECK-NEXT: br label [[MIDDLE_BLOCK:%.*]]
382-
; CHECK: middle.block:
383-
; CHECK-NEXT: br label [[EXIT:%.*]]
384-
; CHECK: scalar.ph:
385344
; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
386345
; CHECK: loop.header:
387-
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
388-
; CHECK-NEXT: br i1 [[C_0]], label [[LOOP_LATCH]], label [[THEN_1:%.*]]
346+
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[SCALAR_PH:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
347+
; CHECK-NEXT: br i1 [[C_0:%.*]], label [[LOOP_LATCH]], label [[THEN_1:%.*]]
389348
; CHECK: then.1:
390349
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[IV]], 2
391350
; CHECK-NEXT: [[OR:%.*]] = and i1 false, [[CMP]]
392351
; CHECK-NEXT: [[COND:%.*]] = select i1 [[OR]], i1 [[C_1:%.*]], i1 false
393352
; CHECK-NEXT: br i1 [[COND]], label [[THEN_2:%.*]], label [[LOOP_LATCH]]
394353
; CHECK: then.2:
395-
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[IV]]
354+
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 [[IV]]
396355
; CHECK-NEXT: store i32 0, ptr [[GEP]], align 4
397356
; CHECK-NEXT: br label [[LOOP_LATCH]]
398357
; CHECK: loop.latch:
399358
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
400359
; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], 3
401-
; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP_HEADER]], !llvm.loop [[LOOP6:![0-9]+]]
360+
; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP_HEADER]]
402361
; CHECK: exit:
403362
; CHECK-NEXT: ret void
404363
;

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