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[Xtensa] Implement Xtensa Region Protection Option and several other small options.
Implement support of the Xtensa Region Protection, Extended L32R, Data Cache, Relocatable Vector and MISC Special Registers Options.
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11 files changed

+284
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lines changed

11 files changed

+284
-4
lines changed

‎llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -114,9 +114,13 @@ static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
114114
}
115115

116116
const MCPhysReg SRDecoderTable[] = {
117-
Xtensa::SAR, 3, Xtensa::ACCLO, 16, Xtensa::ACCHI, 17,
118-
Xtensa::M0, 32, Xtensa::M1, 33, Xtensa::M2, 34,
119-
Xtensa::M3, 35, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73};
117+
Xtensa::LBEG, 0, Xtensa::LEND, 1, Xtensa::LCOUNT, 2,
118+
Xtensa::SAR, 3, Xtensa::BREG, 4, Xtensa::SAR, 3,
119+
Xtensa::LITBASE, 5, Xtensa::ACCLO, 16, Xtensa::ACCHI, 17,
120+
Xtensa::M0, 32, Xtensa::M1, 33, Xtensa::M2, 34,
121+
Xtensa::M3, 35, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73,
122+
Xtensa::MEMCTL, 97, Xtensa::VECBASE, 231, Xtensa::MISC0, 244,
123+
Xtensa::MISC1, 345, Xtensa::MISC2, 246, Xtensa::MISC3, 247};
120124

121125
static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
122126
uint64_t Address,

‎llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -83,6 +83,17 @@ bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits) {
8383
case Xtensa::LEND:
8484
case Xtensa::LCOUNT:
8585
return FeatureBits[Xtensa::FeatureLoop];
86+
case Xtensa::LITBASE:
87+
return FeatureBits[Xtensa::FeatureExtendedL32R];
88+
case Xtensa::MEMCTL:
89+
return FeatureBits[Xtensa::FeatureDataCache];
90+
case Xtensa::MISC0:
91+
case Xtensa::MISC1:
92+
case Xtensa::MISC2:
93+
case Xtensa::MISC3:
94+
return FeatureBits[Xtensa::FeatureMiscSR];
95+
case Xtensa::VECBASE:
96+
return FeatureBits[Xtensa::FeatureRelocatableVector];
8697
case Xtensa::WINDOWBASE:
8798
case Xtensa::WINDOWSTART:
8899
return FeatureBits[Xtensa::FeatureWindowed];

‎llvm/lib/Target/Xtensa/XtensaFeatures.td‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,3 +67,28 @@ def FeatureDiv32 : SubtargetFeature<"div32", "HasDiv32", "true",
6767
"Enable Xtensa Div32 option">;
6868
def HasDiv32 : Predicate<"Subtarget->hasDiv32()">,
6969
AssemblerPredicate<(all_of FeatureDiv32)>;
70+
71+
def FeatureRegionProtection : SubtargetFeature<"regprotect", "HasRegionProtection", "true",
72+
"Enable Xtensa Region Protection option">;
73+
def HasRegionProtection : Predicate<"Subtarget->hasRegionProtection()">,
74+
AssemblerPredicate<(all_of FeatureRegionProtection)>;
75+
76+
def FeatureRelocatableVector : SubtargetFeature<"rvector", "HasRelocatableVector", "true",
77+
"Enable Xtensa Relocatable Vector option">;
78+
def HasRelocatableVector : Predicate<"Subtarget->hasRelocatableVector()">,
79+
AssemblerPredicate<(all_of FeatureRelocatableVector)>;
80+
81+
def FeatureMiscSR : SubtargetFeature<"miscsr", "HasMiscSR", "true",
82+
"Enable Xtensa Miscellaneous SR option">;
83+
def HasMiscSR : Predicate<"Subtarget->hasMiscSR()">,
84+
AssemblerPredicate<(all_of FeatureMiscSR)>;
85+
86+
def FeatureExtendedL32R : SubtargetFeature<"extendedl32r", "HasExtendedL32R", "true",
87+
"Enable Xtensa Extended L32R option">;
88+
def HasExtendedL32R : Predicate<"Subtarget->hasExtendedL32R()">,
89+
AssemblerPredicate<(all_of FeatureExtendedL32R)>;
90+
91+
def FeatureDataCache : SubtargetFeature<"dcache", "HasDataCache", "true",
92+
"Enable Xtensa Data Cache option">;
93+
def HasDataCache : Predicate<"Subtarget->hasDataCache()">,
94+
AssemblerPredicate<(all_of FeatureDataCache)>;

‎llvm/lib/Target/Xtensa/XtensaInstrInfo.td‎

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -986,6 +986,64 @@ let Predicates = [HasDiv32] in {
986986
def REMU : ArithLogic_RRR<0x0E, 0x02, "remu", urem>;
987987
}
988988

989+
//===----------------------------------------------------------------------===//
990+
// Region Protection feature instructions
991+
//===----------------------------------------------------------------------===//
992+
993+
let Predicates = [HasRegionProtection] in {
994+
def IDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs), (ins AR:$s),
995+
"idtlb\t$s", []> {
996+
let r = 0xC;
997+
let t = 0x0;
998+
}
999+
1000+
def IITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1001+
"iitlb\t$s", []> {
1002+
let r = 0x4;
1003+
let t = 0x0;
1004+
}
1005+
1006+
def PDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1007+
"pdtlb\t$t, $s", []> {
1008+
let r = 0xD;
1009+
}
1010+
1011+
def PITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1012+
"pitlb\t$t, $s", []> {
1013+
let r = 0x5;
1014+
}
1015+
1016+
def RDTLB0 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1017+
"rdtlb0\t$t, $s", []> {
1018+
let r = 0xB;
1019+
}
1020+
1021+
def RDTLB1 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1022+
"rdtlb1\t$t, $s", []> {
1023+
let r = 0xF;
1024+
}
1025+
1026+
def RITLB0 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1027+
"ritlb0\t$t, $s", []> {
1028+
let r = 0x3;
1029+
}
1030+
1031+
def RITLB1 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1032+
"ritlb1\t$t, $s", []> {
1033+
let r = 0x7;
1034+
}
1035+
1036+
def WDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1037+
"wdtlb\t$t, $s", []> {
1038+
let r = 0xE;
1039+
}
1040+
1041+
def WITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1042+
"witlb\t$t, $s", []> {
1043+
let r = 0x6;
1044+
}
1045+
}
1046+
9891047
//===----------------------------------------------------------------------===//
9901048
// DSP Instructions
9911049
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/Xtensa/XtensaRegisterInfo.td‎

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -84,10 +84,25 @@ def SAR : SRReg<3, "sar", ["SAR","3"]>;
8484
// Boolean Register
8585
def BREG : SRReg<4, "br", ["BR","4"]>;
8686

87+
// Literal base
88+
def LITBASE : SRReg<5, "litbase", ["LITBASE", "5"]>;
89+
8790
// Windowed Register Option registers
8891
def WINDOWBASE : SRReg<72, "windowbase", ["WINDOWBASE", "72"]>;
8992
def WINDOWSTART : SRReg<73, "windowstart", ["WINDOWSTART", "73"]>;
9093

94+
// Memory Control Register
95+
def MEMCTL : SRReg<97, "memctl", ["MEMCTL", "97"]>;
96+
97+
// Vector base register
98+
def VECBASE : SRReg<231, "vecbase", ["VECBASE", "231"]>;
99+
100+
// Xtensa Miscellaneous SR
101+
def MISC0 : SRReg<244, "misc0", ["MISC0", "244"]>;
102+
def MISC1 : SRReg<245, "misc1", ["MISC1", "245"]>;
103+
def MISC2 : SRReg<246, "misc2", ["MISC2", "246"]>;
104+
def MISC3 : SRReg<247, "misc3", ["MISC3", "247"]>;
105+
91106
// MAC16 Option registers
92107
def ACCLO : SRReg<16, "acclo", ["ACCLO", "16"]>;
93108
def ACCHI : SRReg<17, "acchi", ["ACCHI", "17"]>;
@@ -101,7 +116,8 @@ def MR23 : RegisterClass<"Xtensa", [i32], 32, (add M2, M3)>;
101116
def MR : RegisterClass<"Xtensa", [i32], 32, (add MR01, MR23)>;
102117

103118
def SR : RegisterClass<"Xtensa", [i32], 32, (add
104-
LBEG, LEND, LCOUNT, SAR, BREG, MR, WINDOWBASE, WINDOWSTART)>;
119+
LBEG, LEND, LCOUNT, SAR, BREG, LITBASE, MR, WINDOWBASE, WINDOWSTART,
120+
MEMCTL, VECBASE, MISC0, MISC1, MISC2, MISC3)>;
105121

106122
//===----------------------------------------------------------------------===//
107123
// Boolean registers

‎llvm/lib/Target/Xtensa/XtensaSubtarget.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,11 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
7777
bool hasMul32() const { return HasMul32; }
7878
bool hasMul32High() const { return HasMul32High; }
7979
bool hasDiv32() const { return HasDiv32; }
80+
bool hasRegionProtection() const { return HasRegionProtection; }
81+
bool hasRelocatableVector() const { return HasRelocatableVector; }
82+
bool hasMiscSR() const { return HasMiscSR; }
83+
bool hasExtendedL32R() const { return HasExtendedL32R; }
84+
bool hasDataCache() const { return HasDataCache; }
8085
bool isWindowedABI() const { return hasWindowed(); }
8186

8287
// Automatically generated by tblgen.

‎llvm/test/MC/Xtensa/dcache.s‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
# RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+dcache \
2+
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
3+
4+
.align 4
5+
6+
# Instruction format RSR
7+
# CHECK-INST: xsr a3, memctl
8+
# CHECK: # encoding: [0x30,0x61,0x61]
9+
xsr a3, memctl
10+
11+
# CHECK-INST: xsr a3, memctl
12+
# CHECK: # encoding: [0x30,0x61,0x61]
13+
xsr.memctl a3
14+
15+
# CHECK-INST: xsr a3, memctl
16+
# CHECK: # encoding: [0x30,0x61,0x61]
17+
xsr a3, 97

‎llvm/test/MC/Xtensa/extendedl32r.s‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
# RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+extendedl32r \
2+
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
3+
4+
.align 4
5+
6+
# Instruction format RSR
7+
# CHECK-INST: xsr a3, litbase
8+
# CHECK: # encoding: [0x30,0x05,0x61]
9+
xsr a3, litbase
10+
11+
# CHECK-INST: xsr a3, litbase
12+
# CHECK: # encoding: [0x30,0x05,0x61]
13+
xsr.litbase a3
14+
15+
# CHECK-INST: xsr a3, litbase
16+
# CHECK: # encoding: [0x30,0x05,0x61]
17+
xsr a3, 5

‎llvm/test/MC/Xtensa/miscsr.s‎

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
1+
# RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+miscsr \
2+
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
3+
4+
.align 4
5+
6+
# Instruction format RSR
7+
# CHECK-INST: xsr a3, misc0
8+
# CHECK: # encoding: [0x30,0xf4,0x61]
9+
xsr a3, misc0
10+
11+
# CHECK-INST: xsr a3, misc0
12+
# CHECK: # encoding: [0x30,0xf4,0x61]
13+
xsr.misc0 a3
14+
15+
# CHECK-INST: xsr a3, misc0
16+
# CHECK: # encoding: [0x30,0xf4,0x61]
17+
xsr a3, 244
18+
19+
# Instruction format RSR
20+
# CHECK-INST: xsr a3, misc1
21+
# CHECK: # encoding: [0x30,0xf5,0x61]
22+
xsr a3, misc1
23+
24+
# CHECK-INST: xsr a3, misc1
25+
# CHECK: # encoding: [0x30,0xf5,0x61]
26+
xsr.misc1 a3
27+
28+
# CHECK-INST: xsr a3, misc1
29+
# CHECK: # encoding: [0x30,0xf5,0x61]
30+
xsr a3, 245
31+
32+
# Instruction format RSR
33+
# CHECK-INST: xsr a3, misc2
34+
# CHECK: # encoding: [0x30,0xf6,0x61]
35+
xsr a3, misc2
36+
37+
# CHECK-INST: xsr a3, misc2
38+
# CHECK: # encoding: [0x30,0xf6,0x61]
39+
xsr.misc2 a3
40+
41+
# CHECK-INST: xsr a3, misc2
42+
# CHECK: # encoding: [0x30,0xf6,0x61]
43+
xsr a3, 246
44+
45+
# Instruction format RSR
46+
# CHECK-INST: xsr a3, misc3
47+
# CHECK: # encoding: [0x30,0xf7,0x61]
48+
xsr a3, misc3
49+
50+
# CHECK-INST: xsr a3, misc3
51+
# CHECK: # encoding: [0x30,0xf7,0x61]
52+
xsr.misc3 a3
53+
54+
# CHECK-INST: xsr a3, misc3
55+
# CHECK: # encoding: [0x30,0xf7,0x61]
56+
xsr a3, 247

‎llvm/test/MC/Xtensa/region_protect.s‎

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,54 @@
1+
# RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+regprotect \
2+
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
3+
4+
.align 4
5+
6+
# Instruction format RRR
7+
# CHECK-INST: idtlb a3
8+
# CHECK: encoding: [0x00,0xc3,0x50]
9+
idtlb a3
10+
11+
# Instruction format RRR
12+
# CHECK-INST: iitlb a3
13+
# CHECK: encoding: [0x00,0x43,0x50]
14+
iitlb a3
15+
16+
# Instruction format RRR
17+
# CHECK-INST: pdtlb a3, a4
18+
# CHECK: encoding: [0x30,0xd4,0x50]
19+
pdtlb a3, a4
20+
21+
# Instruction format RRR
22+
# CHECK-INST: pitlb a3, a4
23+
# CHECK: encoding: [0x30,0x54,0x50]
24+
pitlb a3, a4
25+
26+
# Instruction format RRR
27+
# CHECK-INST: rdtlb0 a3, a4
28+
# CHECK: encoding: [0x30,0xb4,0x50]
29+
rdtlb0 a3, a4
30+
31+
# Instruction format RRR
32+
# CHECK-INST: rdtlb1 a3, a4
33+
# CHECK: encoding: [0x30,0xf4,0x50]
34+
rdtlb1 a3, a4
35+
36+
# Instruction format RRR
37+
# CHECK-INST: ritlb0 a3, a4
38+
# CHECK: encoding: [0x30,0x34,0x50]
39+
ritlb0 a3, a4
40+
41+
# Instruction format RRR
42+
# CHECK-INST: ritlb1 a3, a4
43+
# CHECK: encoding: [0x30,0x74,0x50]
44+
ritlb1 a3, a4
45+
46+
# Instruction format RRR
47+
# CHECK-INST: wdtlb a3, a4
48+
# CHECK: encoding: [0x30,0xe4,0x50]
49+
wdtlb a3, a4
50+
51+
# Instruction format RRR
52+
# CHECK-INST: witlb a3, a4
53+
# CHECK: encoding: [0x30,0x64,0x50]
54+
witlb a3, a4

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