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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 |
| 2 | +; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s |
| 3 | +define amdgpu_ps i64 @ordertest(i64 inreg %val0) { |
| 4 | +; CHECK-LABEL: ordertest: |
| 5 | +; CHECK: ; %bb.0: |
| 6 | +; CHECK-NEXT: s_lshr_b32 s0, s1, 2 |
| 7 | +; CHECK-NEXT: s_mov_b32 s1, 0 |
| 8 | +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 |
| 9 | +; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0 |
| 10 | +; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[2:3] |
| 11 | +; CHECK-NEXT: v_lshrrev_b64 v[0:1], v2, s[0:1] |
| 12 | +; CHECK-NEXT: v_xor_b32_e32 v0, v2, v0 |
| 13 | +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 |
| 14 | +; CHECK-NEXT: ; return to shader part epilog |
| 15 | + %shl = lshr i64 %val0, 34 |
| 16 | + %result = and i64 %shl, 4294967295 |
| 17 | + %cmp = icmp ne i64 %result, 0 |
| 18 | + %zext = zext i1 %cmp to i64 |
| 19 | + %param0 = lshr i64 %shl, %zext |
| 20 | + %param = and i64 %param0, 4294967295 |
| 21 | + %xory = xor i64 %zext, %param |
| 22 | + ret i64 %xory |
| 23 | +} |
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