Check instruction by MCInstrDesc::getSchedClass() == 0 and add testcase

Author: tclin914

llvm/include/llvm/MC/MCInstrDesc.h

@@ -188,7 +188,6 @@ enum Flag {
   Trap,
   VariadicOpsAreDefs,
   Authenticated,
-  HasNoSchedulingInfo,
 };
 } // namespace MCID
 
@@ -431,11 +430,6 @@ class MCInstrDesc {
     return Flags & (1ULL << MCID::Authenticated);
   }
 
-  /// Return true if this instruction has no scheduling info.
-  bool hasNoSchedulingInfo() const {
-    return Flags & (1ULL << MCID::HasNoSchedulingInfo);
-  }
-
   //===--------------------------------------------------------------------===//
   // Side Effect Analysis
   //===--------------------------------------------------------------------===//

llvm/test/tools/llvm-exegesis/RISCV/unsupported-opcode.s

@@ -0,0 +1,3 @@
+# RUN: llvm-exegesis -mtriple=riscv64-unknown-linux-gnu -mcpu=generic --benchmark-phase=assemble-measured-code -mode=inverse_throughput -opcode-name=InsnB 2>&1 | FileCheck %s
+
+CHECK: Unsupported opcode: No Sched Class

llvm/tools/llvm-exegesis/lib/Target.cpp

@@ -45,8 +45,8 @@ ExegesisTarget::getIgnoredOpcodeReasonOrNull(const LLVMState &State,
     return "Unsupported opcode: isBranch/isIndirectBranch";
   if (InstrDesc.isCall() || InstrDesc.isReturn())
     return "Unsupported opcode: isCall/isReturn";
-  if (InstrDesc.hasNoSchedulingInfo())
-    return "Unsupported opcode: hasNoSchedulingInfo";
+  if (InstrDesc.getSchedClass() == 0)
+    return "Unsupported opcode: No Sched Class";
   return nullptr;
 }
 

llvm/utils/TableGen/InstrInfoEmitter.cpp

@@ -1199,8 +1199,6 @@ void InstrInfoEmitter::emitRecord(
     OS << "|(1ULL<<MCID::VariadicOpsAreDefs)";
   if (Inst.isAuthenticated)
     OS << "|(1ULL<<MCID::Authenticated)";
-  if (Inst.hasNoSchedulingInfo)
-    OS << "|(1ULL<<MCID::HasNoSchedulingInfo)";
 
   // Emit all of the target-specific flags...
   const BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");