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1 parent 0f09f2c commit e51ea1cCopy full SHA for e51ea1c
llvm/test/CodeGen/RISCV/xandesbfhcvt.ll
@@ -4,8 +4,6 @@
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; RUN: llc -mtriple=riscv64 -mattr=+xandesbfhcvt -target-abi lp64f \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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-declare bfloat @llvm.riscv.nds.fcvt.bf16.s(float)
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-
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define float @fcvt_s_bf16(bfloat %a) nounwind {
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; CHECK-LABEL: fcvt_s_bf16:
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; CHECK: # %bb.0:
@@ -15,8 +13,6 @@ define float @fcvt_s_bf16(bfloat %a) nounwind {
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ret float %1
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}
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-declare float @llvm.riscv.nds.fcvt.s.bf16(bfloat)
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define bfloat @fcvt_bf16_s(float %a) nounwind {
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; CHECK-LABEL: fcvt_bf16_s:
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