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[VPlan] optimize BranchCond for canonical WidenIntOrFpInduction recipe
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9 files changed

+201
-441
lines changed

9 files changed

+201
-441
lines changed

‎llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp‎

Lines changed: 14 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1498,10 +1498,21 @@ static bool simplifyBranchConditionForVFAndUF(VPlan &Plan, ElementCount BestVF,
14981498
// the region, otherwise replace the terminator controlling the latch with
14991499
// (BranchOnCond true).
15001500
auto *Header = cast<VPBasicBlock>(VectorRegion->getEntry());
1501-
if (all_of(Header->phis(),
1502-
IsaPred<VPCanonicalIVPHIRecipe, VPEVLBasedIVPHIRecipe,
1503-
VPFirstOrderRecurrencePHIRecipe, VPPhi>)) {
1501+
if (all_of(Header->phis(), [](VPRecipeBase &Phi) {
1502+
if (auto *R = dyn_cast<VPWidenIntOrFpInductionRecipe>(&Phi))
1503+
return R->isCanonical();
1504+
return isa<VPCanonicalIVPHIRecipe, VPEVLBasedIVPHIRecipe,
1505+
VPFirstOrderRecurrencePHIRecipe, VPPhi>(&Phi);
1506+
})) {
15041507
for (VPRecipeBase &HeaderR : make_early_inc_range(Header->phis())) {
1508+
if (auto *R = dyn_cast<VPWidenIntOrFpInductionRecipe>(&HeaderR)) {
1509+
VPBuilder Builder(Plan.getVectorPreheader());
1510+
VPValue *StepV = Builder.createNaryOp(VPInstruction::StepVector, {},
1511+
R->getScalarType());
1512+
HeaderR.getVPSingleValue()->replaceAllUsesWith(StepV);
1513+
HeaderR.eraseFromParent();
1514+
continue;
1515+
}
15051516
auto *Phi = cast<VPPhiAccessors>(&HeaderR);
15061517
HeaderR.getVPSingleValue()->replaceAllUsesWith(Phi->getIncomingValue(0));
15071518
HeaderR.eraseFromParent();

‎llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll‎

Lines changed: 60 additions & 120 deletions
Large diffs are not rendered by default.

‎llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-remove-loop-region.ll‎

Lines changed: 11 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -48,14 +48,9 @@ define void @load_store_interleave_group_tc_2(ptr noalias %data) {
4848
; VF4: [[VECTOR_PH]]:
4949
; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
5050
; VF4: [[VECTOR_BODY]]:
51-
; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE6:.*]] ]
52-
; VF4-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ <i8 0, i8 1, i8 2, i8 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE6]] ]
53-
; VF4-NEXT: [[TMP0:%.*]] = icmp ule <4 x i8> [[VEC_IND]], splat (i8 1)
54-
; VF4-NEXT: [[TMP1:%.*]] = extractelement <4 x i1> [[TMP0]], i32 0
55-
; VF4-NEXT: br i1 [[TMP1]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
51+
; VF4-NEXT: br i1 true, label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
5652
; VF4: [[PRED_STORE_IF]]:
57-
; VF4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 0
58-
; VF4-NEXT: [[TMP3:%.*]] = shl nsw i64 [[TMP2]], 1
53+
; VF4-NEXT: [[TMP3:%.*]] = shl nsw i64 0, 1
5954
; VF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP3]]
6055
; VF4-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
6156
; VF4-NEXT: store i64 [[TMP5]], ptr [[TMP4]], align 8
@@ -65,11 +60,9 @@ define void @load_store_interleave_group_tc_2(ptr noalias %data) {
6560
; VF4-NEXT: store i64 [[TMP8]], ptr [[TMP7]], align 8
6661
; VF4-NEXT: br label %[[PRED_STORE_CONTINUE]]
6762
; VF4: [[PRED_STORE_CONTINUE]]:
68-
; VF4-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP0]], i32 1
69-
; VF4-NEXT: br i1 [[TMP9]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]
63+
; VF4-NEXT: br i1 true, label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]
7064
; VF4: [[PRED_STORE_IF1]]:
71-
; VF4-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 1
72-
; VF4-NEXT: [[TMP11:%.*]] = shl nsw i64 [[TMP10]], 1
65+
; VF4-NEXT: [[TMP11:%.*]] = shl nsw i64 1, 1
7366
; VF4-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP11]]
7467
; VF4-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8
7568
; VF4-NEXT: store i64 [[TMP13]], ptr [[TMP12]], align 8
@@ -79,11 +72,9 @@ define void @load_store_interleave_group_tc_2(ptr noalias %data) {
7972
; VF4-NEXT: store i64 [[TMP16]], ptr [[TMP15]], align 8
8073
; VF4-NEXT: br label %[[PRED_STORE_CONTINUE2]]
8174
; VF4: [[PRED_STORE_CONTINUE2]]:
82-
; VF4-NEXT: [[TMP17:%.*]] = extractelement <4 x i1> [[TMP0]], i32 2
83-
; VF4-NEXT: br i1 [[TMP17]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]
75+
; VF4-NEXT: br i1 false, label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]
8476
; VF4: [[PRED_STORE_IF3]]:
85-
; VF4-NEXT: [[TMP18:%.*]] = add i64 [[INDEX]], 2
86-
; VF4-NEXT: [[TMP19:%.*]] = shl nsw i64 [[TMP18]], 1
77+
; VF4-NEXT: [[TMP19:%.*]] = shl nsw i64 2, 1
8778
; VF4-NEXT: [[TMP20:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP19]]
8879
; VF4-NEXT: [[TMP21:%.*]] = load i64, ptr [[TMP20]], align 8
8980
; VF4-NEXT: store i64 [[TMP21]], ptr [[TMP20]], align 8
@@ -93,11 +84,9 @@ define void @load_store_interleave_group_tc_2(ptr noalias %data) {
9384
; VF4-NEXT: store i64 [[TMP24]], ptr [[TMP23]], align 8
9485
; VF4-NEXT: br label %[[PRED_STORE_CONTINUE4]]
9586
; VF4: [[PRED_STORE_CONTINUE4]]:
96-
; VF4-NEXT: [[TMP25:%.*]] = extractelement <4 x i1> [[TMP0]], i32 3
97-
; VF4-NEXT: br i1 [[TMP25]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6]]
87+
; VF4-NEXT: br i1 false, label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]
9888
; VF4: [[PRED_STORE_IF5]]:
99-
; VF4-NEXT: [[TMP26:%.*]] = add i64 [[INDEX]], 3
100-
; VF4-NEXT: [[TMP27:%.*]] = shl nsw i64 [[TMP26]], 1
89+
; VF4-NEXT: [[TMP27:%.*]] = shl nsw i64 3, 1
10190
; VF4-NEXT: [[TMP28:%.*]] = getelementptr inbounds i64, ptr [[DATA]], i64 [[TMP27]]
10291
; VF4-NEXT: [[TMP29:%.*]] = load i64, ptr [[TMP28]], align 8
10392
; VF4-NEXT: store i64 [[TMP29]], ptr [[TMP28]], align 8
@@ -107,9 +96,7 @@ define void @load_store_interleave_group_tc_2(ptr noalias %data) {
10796
; VF4-NEXT: store i64 [[TMP32]], ptr [[TMP31]], align 8
10897
; VF4-NEXT: br label %[[PRED_STORE_CONTINUE6]]
10998
; VF4: [[PRED_STORE_CONTINUE6]]:
110-
; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
111-
; VF4-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND]], splat (i8 4)
112-
; VF4-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
99+
; VF4-NEXT: br label %[[MIDDLE_BLOCK:.*]]
113100
; VF4: [[MIDDLE_BLOCK]]:
114101
; VF4-NEXT: br label %[[EXIT:.*]]
115102
; VF4: [[SCALAR_PH]]:
@@ -126,7 +113,7 @@ define void @load_store_interleave_group_tc_2(ptr noalias %data) {
126113
; VF4-NEXT: store i64 [[L_1]], ptr [[DATA_1]], align 8
127114
; VF4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
128115
; VF4-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 2
129-
; VF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
116+
; VF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP0:![0-9]+]]
130117
; VF4: [[EXIT]]:
131118
; VF4-NEXT: ret void
132119
;
@@ -318,7 +305,7 @@ define void @test_complex_add_float_tc_4(ptr %res, ptr noalias %A, ptr noalias %
318305
; VF4-NEXT: store float [[ADD_1]], ptr [[GEP_RES_1]], align 4
319306
; VF4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
320307
; VF4-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 4
321-
; VF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
308+
; VF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
322309
; VF4: [[EXIT]]:
323310
; VF4-NEXT: ret void
324311
;

‎llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll‎

Lines changed: 16 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -71,46 +71,37 @@ define void @redundant_or_1(ptr %dst, i1 %c.0, i1 %c.1) {
7171
; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT1]], <4 x i1> poison, <4 x i32> zeroinitializer
7272
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
7373
; CHECK: vector.body:
74-
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE8:%.*]] ]
75-
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ <i8 0, i8 1, i8 2, i8 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE8]] ]
76-
; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <4 x i8> [[VEC_IND]], splat (i8 2)
77-
; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i1> [[TMP0]], <4 x i1> zeroinitializer
74+
; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i1> [[TMP0]], <4 x i1> zeroinitializer
7875
; CHECK-NEXT: [[TMP5:%.*]] = select <4 x i1> [[TMP2]], <4 x i1> [[BROADCAST_SPLAT2]], <4 x i1> zeroinitializer
7976
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i1> [[TMP5]], i32 0
8077
; CHECK-NEXT: br i1 [[TMP6]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
8178
; CHECK: pred.store.if:
82-
; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[INDEX]], 0
83-
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 [[TMP7]]
79+
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 0
8480
; CHECK-NEXT: store i32 0, ptr [[TMP8]], align 4
8581
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]]
8682
; CHECK: pred.store.continue:
8783
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP5]], i32 1
8884
; CHECK-NEXT: br i1 [[TMP9]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]]
8985
; CHECK: pred.store.if3:
90-
; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[INDEX]], 1
91-
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[TMP10]]
86+
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 1
9287
; CHECK-NEXT: store i32 0, ptr [[TMP11]], align 4
9388
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]]
9489
; CHECK: pred.store.continue4:
9590
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i1> [[TMP5]], i32 2
9691
; CHECK-NEXT: br i1 [[TMP12]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]]
9792
; CHECK: pred.store.if5:
98-
; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[INDEX]], 2
99-
; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[TMP13]]
93+
; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 2
10094
; CHECK-NEXT: store i32 0, ptr [[TMP14]], align 4
10195
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]]
10296
; CHECK: pred.store.continue6:
10397
; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i1> [[TMP5]], i32 3
104-
; CHECK-NEXT: br i1 [[TMP15]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8]]
98+
; CHECK-NEXT: br i1 [[TMP15]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]]
10599
; CHECK: pred.store.if7:
106-
; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[INDEX]], 3
107-
; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[TMP16]]
100+
; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 3
108101
; CHECK-NEXT: store i32 0, ptr [[TMP17]], align 4
109102
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE8]]
110103
; CHECK: pred.store.continue8:
111-
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
112-
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND]], splat (i8 4)
113-
; CHECK-NEXT: br i1 true, label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
104+
; CHECK-NEXT: br label [[MIDDLE_BLOCK:%.*]]
114105
; CHECK: middle.block:
115106
; CHECK-NEXT: br label [[EXIT:%.*]]
116107
; CHECK: scalar.ph:
@@ -130,7 +121,7 @@ define void @redundant_or_1(ptr %dst, i1 %c.0, i1 %c.1) {
130121
; CHECK: loop.latch:
131122
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
132123
; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], 3
133-
; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP_HEADER]], !llvm.loop [[LOOP4:![0-9]+]]
124+
; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
134125
; CHECK: exit:
135126
; CHECK-NEXT: ret void
136127
;
@@ -173,46 +164,37 @@ define void @redundant_or_2(ptr %dst, i1 %c.0, i1 %c.1) {
173164
; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT1]], <4 x i1> poison, <4 x i32> zeroinitializer
174165
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
175166
; CHECK: vector.body:
176-
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE8:%.*]] ]
177-
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ <i8 0, i8 1, i8 2, i8 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE8]] ]
178-
; CHECK-NEXT: [[TMP2:%.*]] = icmp ule <4 x i8> [[VEC_IND]], splat (i8 2)
179-
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP2]], <4 x i1> [[TMP0]], <4 x i1> zeroinitializer
167+
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i1> [[TMP0]], <4 x i1> zeroinitializer
180168
; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP3]], <4 x i1> [[BROADCAST_SPLAT2]], <4 x i1> zeroinitializer
181169
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP4]], i32 0
182170
; CHECK-NEXT: br i1 [[TMP5]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
183171
; CHECK: pred.store.if:
184-
; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[INDEX]], 0
185-
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 [[TMP6]]
172+
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 0
186173
; CHECK-NEXT: store i32 0, ptr [[TMP7]], align 4
187174
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]]
188175
; CHECK: pred.store.continue:
189176
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP4]], i32 1
190177
; CHECK-NEXT: br i1 [[TMP8]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]]
191178
; CHECK: pred.store.if3:
192-
; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[INDEX]], 1
193-
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[TMP9]]
179+
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 1
194180
; CHECK-NEXT: store i32 0, ptr [[TMP10]], align 4
195181
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]]
196182
; CHECK: pred.store.continue4:
197183
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP4]], i32 2
198184
; CHECK-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]]
199185
; CHECK: pred.store.if5:
200-
; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[INDEX]], 2
201-
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[TMP12]]
186+
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 2
202187
; CHECK-NEXT: store i32 0, ptr [[TMP13]], align 4
203188
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]]
204189
; CHECK: pred.store.continue6:
205190
; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i1> [[TMP4]], i32 3
206-
; CHECK-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8]]
191+
; CHECK-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]]
207192
; CHECK: pred.store.if7:
208-
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[INDEX]], 3
209-
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 [[TMP15]]
193+
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[DST]], i32 3
210194
; CHECK-NEXT: store i32 0, ptr [[TMP16]], align 4
211195
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE8]]
212196
; CHECK: pred.store.continue8:
213-
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
214-
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND]], splat (i8 4)
215-
; CHECK-NEXT: br i1 true, label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
197+
; CHECK-NEXT: br label [[MIDDLE_BLOCK:%.*]]
216198
; CHECK: middle.block:
217199
; CHECK-NEXT: br label [[EXIT:%.*]]
218200
; CHECK: scalar.ph:
@@ -232,7 +214,7 @@ define void @redundant_or_2(ptr %dst, i1 %c.0, i1 %c.1) {
232214
; CHECK: loop.latch:
233215
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
234216
; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], 3
235-
; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP_HEADER]], !llvm.loop [[LOOP6:![0-9]+]]
217+
; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP_HEADER]], !llvm.loop [[LOOP4:![0-9]+]]
236218
; CHECK: exit:
237219
; CHECK-NEXT: ret void
238220
;

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