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[RISCV][TTI] Add cost model for ROTL/ROTR (#170824)
A funnel shift with the same first two operands is a rotate. When `Zbb/Zbkb` is enabled we can use the `ROL(W)/ROR(I)(W)` instruction to represent this. Add cost model support for this. Similar to #169335 for AArch64.
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‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp‎

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@@ -1559,6 +1559,23 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
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}
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break;
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}
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case Intrinsic::fshl:
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case Intrinsic::fshr: {
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if (ICA.getArgs().empty())
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break;
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// Funnel-shifts are ROTL/ROTR when the first and second operand are equal.
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// When Zbb/Zbkb is enabled we can use a single ROL(W)/ROR(I)(W)
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// instruction.
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if ((ST->hasStdExtZbb() || ST->hasStdExtZbkb()) && RetTy->isIntegerTy() &&
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ICA.getArgs()[0] == ICA.getArgs()[1] &&
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(RetTy->getIntegerBitWidth() == 32 ||
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RetTy->getIntegerBitWidth() == 64) &&
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RetTy->getIntegerBitWidth() <= ST->getXLen()) {
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return 1;
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}
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break;
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}
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case Intrinsic::get_active_lane_mask: {
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if (ST->hasVInstructions()) {
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Type *ExpRetTy = VectorType::get(

‎llvm/test/Analysis/CostModel/RISCV/fshl_fshr.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=riscv32 < %s | FileCheck %s --check-prefix=RV32
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; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=riscv64 < %s | FileCheck %s --check-prefix=RV64
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; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=riscv32 -mattr=+zbb < %s | FileCheck %s --check-prefix=RV32ZBB
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; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mtriple=riscv64 -mattr=+zbb < %s | FileCheck %s --check-prefix=RV64ZBB
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define i32 @rotl_i32_3rd_arg_const(i32 %a) {
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; RV32-LABEL: 'rotl_i32_3rd_arg_const'
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; RV32-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
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; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
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;
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; RV64-LABEL: 'rotl_i32_3rd_arg_const'
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; RV64-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
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; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
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;
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; RV32ZBB-LABEL: 'rotl_i32_3rd_arg_const'
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; RV32ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
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; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
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;
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; RV64ZBB-LABEL: 'rotl_i32_3rd_arg_const'
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; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
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; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
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;
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entry:
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%r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 9)
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ret i32 %r
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}
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define i32 @rotl_i32_3rd_arg_var(i32 %a, i32 %c) {
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; RV32-LABEL: 'rotl_i32_3rd_arg_var'
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; RV32-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
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; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
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;
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; RV64-LABEL: 'rotl_i32_3rd_arg_var'
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; RV64-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
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; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
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;
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; RV32ZBB-LABEL: 'rotl_i32_3rd_arg_var'
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; RV32ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
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; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
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;
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; RV64ZBB-LABEL: 'rotl_i32_3rd_arg_var'
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; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
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; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
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;
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entry:
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%r = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %c)
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ret i32 %r
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}
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define i64 @rotl_i64_3rd_arg_const(i64 %a) {
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; RV32-LABEL: 'rotl_i64_3rd_arg_const'
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; RV32-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
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; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
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;
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; RV64-LABEL: 'rotl_i64_3rd_arg_const'
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; RV64-NEXT: Cost Model: Found costs of 4 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
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; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
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;
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; RV32ZBB-LABEL: 'rotl_i64_3rd_arg_const'
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; RV32ZBB-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
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; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
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;
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; RV64ZBB-LABEL: 'rotl_i64_3rd_arg_const'
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; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
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; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
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;
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entry:
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%r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 9)
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ret i64 %r
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}
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define i64 @rotl_i64_3rd_arg_var(i64 %a, i64 %c) {
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; RV32-LABEL: 'rotl_i64_3rd_arg_var'
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; RV32-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
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; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
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;
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; RV64-LABEL: 'rotl_i64_3rd_arg_var'
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; RV64-NEXT: Cost Model: Found costs of 5 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
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; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
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;
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; RV32ZBB-LABEL: 'rotl_i64_3rd_arg_var'
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; RV32ZBB-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
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; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
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;
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; RV64ZBB-LABEL: 'rotl_i64_3rd_arg_var'
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; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
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; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
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;
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entry:
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%r = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %c)
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ret i64 %r
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}
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define i32 @rotr_i32_3rd_arg_const(i32 %a) {
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; RV32-LABEL: 'rotr_i32_3rd_arg_const'
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; RV32-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
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; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
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;
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; RV64-LABEL: 'rotr_i32_3rd_arg_const'
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; RV64-NEXT: Cost Model: Found costs of 4 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
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; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
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;
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; RV32ZBB-LABEL: 'rotr_i32_3rd_arg_const'
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; RV32ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
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; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
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;
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; RV64ZBB-LABEL: 'rotr_i32_3rd_arg_const'
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; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
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; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
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;
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entry:
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%r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 9)
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ret i32 %r
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}
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define i32 @rotr_i32_3rd_arg_var(i32 %a, i32 %c) {
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; RV32-LABEL: 'rotr_i32_3rd_arg_var'
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; RV32-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
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; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
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;
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; RV64-LABEL: 'rotr_i32_3rd_arg_var'
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; RV64-NEXT: Cost Model: Found costs of 5 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
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; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
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;
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; RV32ZBB-LABEL: 'rotr_i32_3rd_arg_var'
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; RV32ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
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; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
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;
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; RV64ZBB-LABEL: 'rotr_i32_3rd_arg_var'
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; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
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; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 %r
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;
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entry:
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%r = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %c)
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ret i32 %r
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}
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define i64 @rotr_i64_3rd_arg_const(i64 %a) {
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; RV32-LABEL: 'rotr_i64_3rd_arg_const'
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; RV32-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
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; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
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;
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; RV64-LABEL: 'rotr_i64_3rd_arg_const'
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; RV64-NEXT: Cost Model: Found costs of 4 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
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; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
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;
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; RV32ZBB-LABEL: 'rotr_i64_3rd_arg_const'
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; RV32ZBB-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
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; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
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;
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; RV64ZBB-LABEL: 'rotr_i64_3rd_arg_const'
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; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
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; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
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;
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entry:
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%r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 9)
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ret i64 %r
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}
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define i64 @rotr_i64_3rd_arg_var(i64 %a, i64 %c) {
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; RV32-LABEL: 'rotr_i64_3rd_arg_var'
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; RV32-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
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; RV32-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
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;
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; RV64-LABEL: 'rotr_i64_3rd_arg_var'
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; RV64-NEXT: Cost Model: Found costs of 5 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
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; RV64-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
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;
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; RV32ZBB-LABEL: 'rotr_i64_3rd_arg_var'
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; RV32ZBB-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
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; RV32ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
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;
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; RV64ZBB-LABEL: 'rotr_i64_3rd_arg_var'
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; RV64ZBB-NEXT: Cost Model: Found costs of 1 for: %r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
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; RV64ZBB-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i64 %r
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;
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entry:
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%r = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %c)
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ret i64 %r
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}

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