Address review comments

Author: sdesmalen-arm

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

@@ -1154,25 +1154,29 @@ bool AArch64RegisterInfo::getRegAllocationHints(
 
   // For predicated SVE instructions where the inactive lanes are undef,
   // pick a destination register that is not unique to avoid introducing
-  // a movprfx to copy a unique register to the destination operand.
+  // a movprfx.
   const TargetRegisterClass *RegRC = MRI.getRegClass(VirtReg);
-  if (ST.isSVEorStreamingSVEAvailable() &&
-      AArch64::ZPRRegClass.hasSubClassEq(RegRC)) {
+  if (AArch64::ZPRRegClass.hasSubClassEq(RegRC)) {
     for (const MachineOperand &DefOp : MRI.def_operands(VirtReg)) {
       const MachineInstr &Def = *DefOp.getParent();
       if (DefOp.isImplicit() ||
           (TII->get(Def.getOpcode()).TSFlags & AArch64::FalseLanesMask) !=
               AArch64::FalseLanesUndef)
         continue;
 
+      unsigned InstFlags =
+          TII->get(AArch64::getSVEPseudoMap(Def.getOpcode())).TSFlags;
+
       for (MCPhysReg R : Order) {
         auto AddHintIfSuitable = [&](MCPhysReg R, const MachineOperand &MO) {
+          // R is a suitable register hint if there exists an operand for the
+          // instruction that is not yet allocated a register or if R matches
+          // one of the other source operands.
           if (!VRM->hasPhys(MO.getReg()) || VRM->getPhys(MO.getReg()) == R)
             Hints.push_back(R);
         };
 
-        unsigned Opcode = AArch64::getSVEPseudoMap(Def.getOpcode());
-        switch (TII->get(Opcode).TSFlags & AArch64::DestructiveInstTypeMask) {
+        switch (InstFlags & AArch64::DestructiveInstTypeMask) {
         default:
           break;
         case AArch64::DestructiveTernaryCommWithRev:
@@ -1187,8 +1191,6 @@ bool AArch64RegisterInfo::getRegAllocationHints(
           break;
         case AArch64::DestructiveBinary:
         case AArch64::DestructiveBinaryImm:
-        case AArch64::DestructiveUnaryPassthru:
-        case AArch64::Destructive2xRegImmUnpred:
           AddHintIfSuitable(R, Def.getOperand(2));
           break;
         }

llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll

@@ -19,9 +19,8 @@ define void @mulvl123_addressing(ptr %src, ptr %dst, i64 %count) #0 {
 ; COMMON-NEXT:    ldr z3, [x0, #3, mul vl]
 ; COMMON-NEXT:    addvl x0, x0, #5
 ; COMMON-NEXT:    umax z0.b, p0/m, z0.b, z1.b
-; COMMON-NEXT:    movprfx z1, z2
-; COMMON-NEXT:    umax z1.b, p0/m, z1.b, z3.b
-; COMMON-NEXT:    umax z0.b, p0/m, z0.b, z1.b
+; COMMON-NEXT:    umax z2.b, p0/m, z2.b, z3.b
+; COMMON-NEXT:    umax z0.b, p0/m, z0.b, z2.b
 ; COMMON-NEXT:    st1b { z0.b }, p0, [x1, x8]
 ; COMMON-NEXT:    incb x8
 ; COMMON-NEXT:    cmp x8, x2