@@ -32,7 +32,8 @@ void VPlanTransforms::introduceTopLevelVectorLoopRegion(
3232 VPBlockUtils::disconnectBlocks (OriginalLatch, HeaderVPBB);
3333 VPBasicBlock *VecPreheader = Plan.createVPBasicBlock (" vector.ph" );
3434 VPBlockUtils::connectBlocks (Plan.getEntry (), VecPreheader);
35- assert (OriginalLatch->getNumSuccessors () == 0 && " expected no predecessors" );
35+ assert (OriginalLatch->getNumSuccessors () == 0 &&
36+ " Plan should end at top level latch" );
3637
3738 // Create SCEV and VPValue for the trip count.
3839 // We use the symbolic max backedge-taken-count, which works also when
@@ -47,11 +48,13 @@ void VPlanTransforms::introduceTopLevelVectorLoopRegion(
4748 vputils::getOrCreateVPValueForSCEVExpr (Plan, TripCount, SE));
4849
4950 // Create VPRegionBlock, with existing header and new empty latch block, to be
50- // filled
51+ // filled.
5152 VPBasicBlock *LatchVPBB = Plan.createVPBasicBlock (" vector.latch" );
5253 VPBlockUtils::insertBlockAfter (LatchVPBB, OriginalLatch);
5354 auto *TopRegion = Plan.createVPRegionBlock (
5455 HeaderVPBB, LatchVPBB, " vector loop" , false /* isReplicator*/ );
56+ // All VPBB's reachable shallowly from HeaderVPBB belong to top level loop,
57+ // because VPlan is expected to end at top level latch.
5558 for (VPBlockBase *VPBB : vp_depth_first_shallow (HeaderVPBB))
5659 VPBB->setParent (TopRegion);
5760
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