Skip to content

Commit e67d2dd

Browse files
committed
fixup! use early out
1 parent fd463cf commit e67d2dd

File tree

1 file changed

+4
-4
lines changed

1 file changed

+4
-4
lines changed

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -330,12 +330,12 @@ bool RISCVLegalizerInfo::legalizeBRJT(MachineInstr &MI,
330330
Register IndexReg = MI.getOperand(2).getReg();
331331
LLT IndexTy = MRI.getType(IndexReg);
332332

333-
if (isPowerOf2_32(EntrySize)) {
334-
auto ShiftAmt = MIRBuilder.buildConstant(IndexTy, Log2_32(EntrySize));
335-
IndexReg = MIRBuilder.buildShl(IndexTy, IndexReg, ShiftAmt).getReg(0);
336-
} else
333+
if (!isPowerOf2_32(EntrySize))
337334
return false;
338335

336+
auto ShiftAmt = MIRBuilder.buildConstant(IndexTy, Log2_32(EntrySize));
337+
IndexReg = MIRBuilder.buildShl(IndexTy, IndexReg, ShiftAmt).getReg(0);
338+
339339
auto Addr = MIRBuilder.buildPtrAdd(PtrTy, PtrReg, IndexReg);
340340

341341
MachineMemOperand *MMO = MF.getMachineMemOperand(

0 commit comments

Comments
 (0)