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[InstCombine] Add mismatched operands test (#157524)
In case I misinterpreted, this can be changed to mismatch the arguments of one of the min calls instead.
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‎llvm/test/Transforms/InstCombine/min-zext.ll‎

Lines changed: 55 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
21
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
32

43
define i32 @test_smin(i32 %arg0, i32 %arg1) {
54
; CHECK-LABEL: define i32 @test_smin(
6-
; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {
7-
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[ARG0]], [[ARG1]]
8-
; CHECK-NEXT: [[V3:%.*]] = zext i1 [[TMP1]] to i32
9-
; CHECK-NEXT: ret i32 [[V3]]
5+
; CHECK-NEXT: %v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)
6+
; CHECK-NEXT: %v1 = add nsw i32 %arg0, 1
7+
; CHECK-NEXT: %v2 = tail call i32 @llvm.smin.i32(i32 %v1, i32 %arg1)
8+
; CHECK-NEXT: %v3 = sub i32 %v2, %v0
9+
; CHECK-NEXT: ret i32 %v3
1010
;
1111
%v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)
1212
%v1 = add nsw i32 %arg0, 1
@@ -17,10 +17,11 @@ define i32 @test_smin(i32 %arg0, i32 %arg1) {
1717

1818
define i32 @test_umin(i32 %arg0, i32 %arg1) {
1919
; CHECK-LABEL: define i32 @test_umin(
20-
; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {
21-
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[ARG0]], [[ARG1]]
22-
; CHECK-NEXT: [[V3:%.*]] = zext i1 [[TMP1]] to i32
23-
; CHECK-NEXT: ret i32 [[V3]]
20+
; CHECK-NEXT: %v0 = tail call i32 @llvm.umin.i32(i32 %arg0, i32 %arg1)
21+
; CHECK-NEXT: %v1 = add nuw i32 %arg0, 1
22+
; CHECK-NEXT: %v2 = tail call i32 @llvm.umin.i32(i32 %v1, i32 %arg1)
23+
; CHECK-NEXT: %v3 = sub i32 %v2, %v0
24+
; CHECK-NEXT: ret i32 %v3
2425
;
2526
%v0 = tail call i32 @llvm.umin.i32(i32 %arg0, i32 %arg1)
2627
%v1 = add nuw i32 %arg0, 1
@@ -31,10 +32,9 @@ define i32 @test_umin(i32 %arg0, i32 %arg1) {
3132

3233
define i1 @test_smin_i1(i1 %arg0, i1 %arg1) {
3334
; CHECK-LABEL: define i1 @test_smin_i1(
34-
; CHECK-SAME: i1 [[ARG0:%.*]], i1 [[ARG1:%.*]]) {
35-
; CHECK-NEXT: [[V0:%.*]] = or i1 [[ARG0]], [[ARG1]]
36-
; CHECK-NEXT: [[V3:%.*]] = xor i1 [[V0]], true
37-
; CHECK-NEXT: ret i1 [[V3]]
35+
; CHECK-NEXT: %v0 = or i1 %arg0, %arg1
36+
; CHECK-NEXT: %v3 = xor i1 %v0, true
37+
; CHECK-NEXT: ret i1 %v3
3838
;
3939
%v0 = tail call i1 @llvm.smin.i1(i1 %arg0, i1 %arg1)
4040
%v1 = add nsw i1 %arg0, 1
@@ -47,50 +47,47 @@ declare void @use(i2)
4747

4848
define i2 @test_smin_use_operands(i2 %arg0, i2 %arg1) {
4949
; CHECK-LABEL: define i2 @test_smin_use_operands(
50-
; CHECK-SAME: i2 [[ARG0:%.*]], i2 [[ARG1:%.*]]) {
51-
; CHECK-NEXT: [[V0:%.*]] = tail call i2 @llvm.smin.i2(i2 [[ARG0]], i2 [[ARG1]])
52-
; CHECK-NEXT: [[V1:%.*]] = add nsw i2 [[ARG0]], 1
53-
; CHECK-NEXT: [[V2:%.*]] = tail call i2 @llvm.smin.i2(i2 [[V1]], i2 [[ARG1]])
54-
; CHECK-NEXT: [[V3:%.*]] = sub i2 [[V2]], [[V0]]
55-
; CHECK-NEXT: call void @use(i2 [[V2]])
56-
; CHECK-NEXT: call void @use(i2 [[V0]])
57-
; CHECK-NEXT: ret i2 [[V3]]
50+
; CHECK-NEXT: %v0 = tail call i2 @llvm.smin.i2(i2 %arg0, i2 %arg1)
51+
; CHECK-NEXT: %v1 = add nsw i2 %arg0, 1
52+
; CHECK-NEXT: %v2 = tail call i2 @llvm.smin.i2(i2 %v1, i2 %arg1)
53+
; CHECK-NEXT: %v3 = sub i2 %v2, %v0
54+
; CHECK-NEXT: call void @use(i2 %v2)
55+
; CHECK-NEXT: call void @use(i2 %v0)
56+
; CHECK-NEXT: ret i2 %v3
5857
;
5958
%v0 = tail call i2 @llvm.smin.i2(i2 %arg0, i2 %arg1)
6059
%v1 = add nsw i2 %arg0, 1
6160
%v2 = tail call i2 @llvm.smin.i2(i2 %v1, i2 %arg1)
62-
%v3 = sub i2 %v2, %v0
61+
%v3 = sub i2 %v2, %v0
6362
call void @use(i2 %v2)
6463
call void @use(i2 %v0)
65-
ret i2 %v3
64+
ret i2 %v3
6665
}
6766

6867
define i2 @test_smin_use_operand(i2 %arg0, i2 %arg1) {
6968
; CHECK-LABEL: define i2 @test_smin_use_operand(
70-
; CHECK-SAME: i2 [[ARG0:%.*]], i2 [[ARG1:%.*]]) {
71-
; CHECK-NEXT: [[V1:%.*]] = add nsw i2 [[ARG0]], 1
72-
; CHECK-NEXT: [[V2:%.*]] = tail call i2 @llvm.smin.i2(i2 [[V1]], i2 [[ARG1]])
73-
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i2 [[ARG0]], [[ARG1]]
74-
; CHECK-NEXT: [[V3:%.*]] = zext i1 [[TMP1]] to i2
75-
; CHECK-NEXT: call void @use(i2 [[V2]])
76-
; CHECK-NEXT: ret i2 [[V3]]
69+
; CHECK-NEXT: %v0 = tail call i2 @llvm.smin.i2(i2 %arg0, i2 %arg1)
70+
; CHECK-NEXT: %v1 = add nsw i2 %arg0, 1
71+
; CHECK-NEXT: %v2 = tail call i2 @llvm.smin.i2(i2 %v1, i2 %arg1)
72+
; CHECK-NEXT: %v3 = sub i2 %v2, %v0
73+
; CHECK-NEXT: call void @use(i2 %v2)
74+
; CHECK-NEXT: ret i2 %v3
7775
;
7876
%v0 = tail call i2 @llvm.smin.i2(i2 %arg0, i2 %arg1)
7977
%v1 = add nsw i2 %arg0, 1
8078
%v2 = tail call i2 @llvm.smin.i2(i2 %v1, i2 %arg1)
81-
%v3 = sub i2 %v2, %v0
79+
%v3 = sub i2 %v2, %v0
8280
call void @use(i2 %v2)
83-
ret i2 %v3
81+
ret i2 %v3
8482
}
8583

8684
define i32 @test_smin_missing_nsw(i32 %arg0, i32 %arg1) {
8785
; CHECK-LABEL: define i32 @test_smin_missing_nsw(
88-
; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {
89-
; CHECK-NEXT: [[V0:%.*]] = tail call i32 @llvm.smin.i32(i32 [[ARG0]], i32 [[ARG1]])
90-
; CHECK-NEXT: [[V1:%.*]] = add i32 [[ARG0]], 1
91-
; CHECK-NEXT: [[V2:%.*]] = tail call i32 @llvm.smin.i32(i32 [[V1]], i32 [[ARG1]])
92-
; CHECK-NEXT: [[V3:%.*]] = sub i32 [[V2]], [[V0]]
93-
; CHECK-NEXT: ret i32 [[V3]]
86+
; CHECK-NEXT: %v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)
87+
; CHECK-NEXT: %v1 = add i32 %arg0, 1
88+
; CHECK-NEXT: %v2 = tail call i32 @llvm.smin.i32(i32 %v1, i32 %arg1)
89+
; CHECK-NEXT: %v3 = sub i32 %v2, %v0
90+
; CHECK-NEXT: ret i32 %v3
9491
;
9592
%v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)
9693
%v1 = add i32 %arg0, 1
@@ -101,16 +98,30 @@ define i32 @test_smin_missing_nsw(i32 %arg0, i32 %arg1) {
10198

10299
define i32 @test_umin_missing_nuw(i32 %arg0, i32 %arg1) {
103100
; CHECK-LABEL: define i32 @test_umin_missing_nuw(
104-
; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {
105-
; CHECK-NEXT: [[V0:%.*]] = tail call i32 @llvm.umin.i32(i32 [[ARG0]], i32 [[ARG1]])
106-
; CHECK-NEXT: [[V1:%.*]] = add i32 [[ARG0]], 1
107-
; CHECK-NEXT: [[V2:%.*]] = tail call i32 @llvm.umin.i32(i32 [[V1]], i32 [[ARG1]])
108-
; CHECK-NEXT: [[V3:%.*]] = sub i32 [[V2]], [[V0]]
109-
; CHECK-NEXT: ret i32 [[V3]]
101+
; CHECK-NEXT: %v0 = tail call i32 @llvm.umin.i32(i32 %arg0, i32 %arg1)
102+
; CHECK-NEXT: %v1 = add i32 %arg0, 1
103+
; CHECK-NEXT: %v2 = tail call i32 @llvm.umin.i32(i32 %v1, i32 %arg1)
104+
; CHECK-NEXT: %v3 = sub i32 %v2, %v0
105+
; CHECK-NEXT: ret i32 %v3
110106
;
111107
%v0 = tail call i32 @llvm.umin.i32(i32 %arg0, i32 %arg1)
112108
%v1 = add i32 %arg0, 1
113109
%v2 = tail call i32 @llvm.umin.i32(i32 %v1, i32 %arg1)
114110
%v3 = sub i32 %v2, %v0
115111
ret i32 %v3
116112
}
113+
114+
define i32 @test_mismatched_operands(i32 %arg0, i32 %arg1) {
115+
; CHECK-LABEL: define i32 @test_mismatched_operands(
116+
; CHECK-NEXT: %v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)
117+
; CHECK-NEXT: %v1 = add nsw i32 %arg0, 1
118+
; CHECK-NEXT: %v2 = tail call i32 @llvm.smin.i32(i32 %v1, i32 %arg1)
119+
; CHECK-NEXT: %v3 = sub i32 %v0, %v2
120+
; CHECK-NEXT: ret i32 %v3
121+
;
122+
%v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)
123+
%v1 = add nsw i32 %arg0, 1
124+
%v2 = tail call i32 @llvm.smin.i32(i32 %v1, i32 %arg1)
125+
%v3 = sub i32 %v0, %v2
126+
ret i32 %v3
127+
}

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