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[AArch64] Support MI and PL (#150314)
Now, why would we want to do this? There are a small number of places where this works: 1. It helps peepholeopt when less flag checking. 2. It allows the folding of things such as x - 0x80000000 < 0 to be folded to cmp x, register holding this value 3. We can refine the other passes over time for this.
1 parent 5ccc734 commit e6b4daf

37 files changed

+446
-331
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3320,7 +3320,8 @@ static bool isZerosVector(const SDNode *N) {
33203320

33213321
/// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
33223322
/// CC
3323-
static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
3323+
static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC,
3324+
SDValue RHS = {}) {
33243325
switch (CC) {
33253326
default:
33263327
llvm_unreachable("Unknown condition code!");
@@ -3331,9 +3332,9 @@ static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
33313332
case ISD::SETGT:
33323333
return AArch64CC::GT;
33333334
case ISD::SETGE:
3334-
return AArch64CC::GE;
3335+
return (RHS && isNullConstant(RHS)) ? AArch64CC::PL : AArch64CC::GE;
33353336
case ISD::SETLT:
3336-
return AArch64CC::LT;
3337+
return (RHS && isNullConstant(RHS)) ? AArch64CC::MI : AArch64CC::LT;
33373338
case ISD::SETLE:
33383339
return AArch64CC::LE;
33393340
case ISD::SETUGT:
@@ -3782,7 +3783,7 @@ static SDValue emitConjunctionRec(SelectionDAG &DAG, SDValue Val,
37823783
SDLoc DL(Val);
37833784
// Determine OutCC and handle FP special case.
37843785
if (isInteger) {
3785-
OutCC = changeIntCCToAArch64CC(CC);
3786+
OutCC = changeIntCCToAArch64CC(CC, RHS);
37863787
} else {
37873788
assert(LHS.getValueType().isFloatingPoint());
37883789
AArch64CC::CondCode ExtraCC;
@@ -4079,7 +4080,7 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
40794080

40804081
if (!Cmp) {
40814082
Cmp = emitComparison(LHS, RHS, CC, DL, DAG);
4082-
AArch64CC = changeIntCCToAArch64CC(CC);
4083+
AArch64CC = changeIntCCToAArch64CC(CC, RHS);
40834084
}
40844085
AArch64cc = getCondCode(DAG, AArch64CC);
40854086
return Cmp;

‎llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Lines changed: 22 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1349,7 +1349,9 @@ AArch64InstructionSelector::emitSelect(Register Dst, Register True,
13491349
return &*SelectInst;
13501350
}
13511351

1352-
static AArch64CC::CondCode changeICMPPredToAArch64CC(CmpInst::Predicate P) {
1352+
static AArch64CC::CondCode
1353+
changeICMPPredToAArch64CC(CmpInst::Predicate P, Register RHS = {},
1354+
MachineRegisterInfo *MRI = nullptr) {
13531355
switch (P) {
13541356
default:
13551357
llvm_unreachable("Unknown condition code!");
@@ -1360,8 +1362,18 @@ static AArch64CC::CondCode changeICMPPredToAArch64CC(CmpInst::Predicate P) {
13601362
case CmpInst::ICMP_SGT:
13611363
return AArch64CC::GT;
13621364
case CmpInst::ICMP_SGE:
1365+
if (RHS && MRI) {
1366+
auto ValAndVReg = getIConstantVRegValWithLookThrough(RHS, *MRI);
1367+
if (ValAndVReg && ValAndVReg->Value == 0)
1368+
return AArch64CC::PL;
1369+
}
13631370
return AArch64CC::GE;
13641371
case CmpInst::ICMP_SLT:
1372+
if (RHS && MRI) {
1373+
auto ValAndVReg = getIConstantVRegValWithLookThrough(RHS, *MRI);
1374+
if (ValAndVReg && ValAndVReg->Value == 0)
1375+
return AArch64CC::MI;
1376+
}
13651377
return AArch64CC::LT;
13661378
case CmpInst::ICMP_SLE:
13671379
return AArch64CC::LE;
@@ -1813,7 +1825,8 @@ bool AArch64InstructionSelector::selectCompareBranchFedByICmp(
18131825
auto &PredOp = ICmp.getOperand(1);
18141826
emitIntegerCompare(ICmp.getOperand(2), ICmp.getOperand(3), PredOp, MIB);
18151827
const AArch64CC::CondCode CC = changeICMPPredToAArch64CC(
1816-
static_cast<CmpInst::Predicate>(PredOp.getPredicate()));
1828+
static_cast<CmpInst::Predicate>(PredOp.getPredicate()),
1829+
ICmp.getOperand(3).getReg(), MIB.getMRI());
18171830
MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC).addMBB(DestMBB);
18181831
I.eraseFromParent();
18191832
return true;
@@ -2510,8 +2523,8 @@ bool AArch64InstructionSelector::earlySelect(MachineInstr &I) {
25102523
emitIntegerCompare(/*LHS=*/Cmp->getOperand(2),
25112524
/*RHS=*/Cmp->getOperand(3), PredOp, MIB);
25122525
auto Pred = static_cast<CmpInst::Predicate>(PredOp.getPredicate());
2513-
const AArch64CC::CondCode InvCC =
2514-
changeICMPPredToAArch64CC(CmpInst::getInversePredicate(Pred));
2526+
const AArch64CC::CondCode InvCC = changeICMPPredToAArch64CC(
2527+
CmpInst::getInversePredicate(Pred), Cmp->getOperand(3).getReg(), &MRI);
25152528
emitCSINC(/*Dst=*/AddDst, /*Src =*/AddLHS, /*Src2=*/AddLHS, InvCC, MIB);
25162529
I.eraseFromParent();
25172530
return true;
@@ -3577,8 +3590,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
35773590
auto &PredOp = I.getOperand(1);
35783591
emitIntegerCompare(I.getOperand(2), I.getOperand(3), PredOp, MIB);
35793592
auto Pred = static_cast<CmpInst::Predicate>(PredOp.getPredicate());
3580-
const AArch64CC::CondCode InvCC =
3581-
changeICMPPredToAArch64CC(CmpInst::getInversePredicate(Pred));
3593+
const AArch64CC::CondCode InvCC = changeICMPPredToAArch64CC(
3594+
CmpInst::getInversePredicate(Pred), I.getOperand(3).getReg(), &MRI);
35823595
emitCSINC(/*Dst=*/I.getOperand(0).getReg(), /*Src1=*/AArch64::WZR,
35833596
/*Src2=*/AArch64::WZR, InvCC, MIB);
35843597
I.eraseFromParent();
@@ -4931,7 +4944,7 @@ MachineInstr *AArch64InstructionSelector::emitConjunctionRec(
49314944
if (Negate)
49324945
CC = CmpInst::getInversePredicate(CC);
49334946
if (isa<GICmp>(Cmp)) {
4934-
OutCC = changeICMPPredToAArch64CC(CC);
4947+
OutCC = changeICMPPredToAArch64CC(CC, RHS, MIB.getMRI());
49354948
} else {
49364949
// Handle special FP cases.
49374950
AArch64CC::CondCode ExtraCC;
@@ -5101,7 +5114,8 @@ bool AArch64InstructionSelector::tryOptSelect(GSelect &I) {
51015114
emitIntegerCompare(CondDef->getOperand(2), CondDef->getOperand(3), PredOp,
51025115
MIB);
51035116
auto Pred = static_cast<CmpInst::Predicate>(PredOp.getPredicate());
5104-
CondCode = changeICMPPredToAArch64CC(Pred);
5117+
CondCode =
5118+
changeICMPPredToAArch64CC(Pred, CondDef->getOperand(3).getReg(), &MRI);
51055119
} else {
51065120
// Get the condition code for the select.
51075121
auto Pred =

‎llvm/test/CodeGen/AArch64/16bit-float-promotion-with-nofp.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ define double @selectcc_f64(double %a, double %b, i32 %d) {
7777
; CHECK-LABEL: selectcc_f64:
7878
; CHECK: // %bb.0: // %entry
7979
; CHECK-NEXT: cmp w2, #0
80-
; CHECK-NEXT: csel x0, x0, x1, lt
80+
; CHECK-NEXT: csel x0, x0, x1, mi
8181
; CHECK-NEXT: ret
8282
entry:
8383
%c = icmp slt i32 %d, 0
@@ -89,7 +89,7 @@ define float @selectcc_f32(float %a, float %b, i32 %d) {
8989
; CHECK-LABEL: selectcc_f32:
9090
; CHECK: // %bb.0: // %entry
9191
; CHECK-NEXT: cmp w2, #0
92-
; CHECK-NEXT: csel w0, w0, w1, lt
92+
; CHECK-NEXT: csel w0, w0, w1, mi
9393
; CHECK-NEXT: ret
9494
entry:
9595
%c = icmp slt i32 %d, 0
@@ -101,7 +101,7 @@ define half @selectcc_f16(half %a, half %b, i32 %d) {
101101
; CHECK-LABEL: selectcc_f16:
102102
; CHECK: // %bb.0: // %entry
103103
; CHECK-NEXT: cmp w2, #0
104-
; CHECK-NEXT: csel w0, w0, w1, lt
104+
; CHECK-NEXT: csel w0, w0, w1, mi
105105
; CHECK-NEXT: ret
106106
entry:
107107
%c = icmp slt i32 %d, 0
@@ -113,7 +113,7 @@ define bfloat @selectcc_bf16(bfloat %a, bfloat %b, i32 %d) {
113113
; CHECK-LABEL: selectcc_bf16:
114114
; CHECK: // %bb.0: // %entry
115115
; CHECK-NEXT: cmp w2, #0
116-
; CHECK-NEXT: csel w0, w0, w1, lt
116+
; CHECK-NEXT: csel w0, w0, w1, mi
117117
; CHECK-NEXT: ret
118118
entry:
119119
%c = icmp slt i32 %d, 0

‎llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,7 @@ body: |
149149
; CHECK-NEXT: {{ $}}
150150
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
151151
; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
152-
; CHECK-NEXT: Bcc 11, %bb.1, implicit $nzcv
152+
; CHECK-NEXT: Bcc 4, %bb.1, implicit $nzcv
153153
; CHECK-NEXT: B %bb.0
154154
; CHECK-NEXT: {{ $}}
155155
; CHECK-NEXT: bb.1:

‎llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -661,7 +661,7 @@ body: |
661661
; SELECT-NEXT: %reg0:gpr32common = COPY $w0
662662
; SELECT-NEXT: %reg1:gpr32 = COPY $w1
663663
; SELECT-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg0, 0, 0, implicit-def $nzcv
664-
; SELECT-NEXT: %select:gpr32 = CSELWr %reg0, %reg1, 11, implicit $nzcv
664+
; SELECT-NEXT: %select:gpr32 = CSELWr %reg0, %reg1, 4, implicit $nzcv
665665
; SELECT-NEXT: $w0 = COPY %select
666666
; SELECT-NEXT: RET_ReallyLR implicit $w0
667667
%reg0:_(s32) = COPY $w0
@@ -699,7 +699,7 @@ body: |
699699
; SELECT-NEXT: {{ $}}
700700
; SELECT-NEXT: %reg0:gpr64 = COPY $x0
701701
; SELECT-NEXT: [[ANDSXri:%[0-9]+]]:gpr64 = ANDSXri %reg0, 8000, implicit-def $nzcv
702-
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
702+
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 4, implicit $nzcv
703703
; SELECT-NEXT: $w0 = COPY %cmp
704704
; SELECT-NEXT: RET_ReallyLR implicit $w0
705705
%reg0:gpr(s64) = COPY $x0

‎llvm/test/CodeGen/AArch64/GlobalISel/select-tbnz-from-cmp.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -166,7 +166,7 @@ body: |
166166
; CHECK-NEXT: {{ $}}
167167
; CHECK-NEXT: %copy:gpr64 = COPY $x0
168168
; CHECK-NEXT: [[ANDSXri:%[0-9]+]]:gpr64 = ANDSXri %copy, 8000, implicit-def $nzcv
169-
; CHECK-NEXT: Bcc 11, %bb.1, implicit $nzcv
169+
; CHECK-NEXT: Bcc 4, %bb.1, implicit $nzcv
170170
; CHECK-NEXT: B %bb.0
171171
; CHECK-NEXT: {{ $}}
172172
; CHECK-NEXT: bb.1:

‎llvm/test/CodeGen/AArch64/arm64-ccmp.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -600,7 +600,7 @@ define i64 @select_noccmp1(i64 %v1, i64 %v2, i64 %v3, i64 %r) {
600600
; CHECK-SD-LABEL: select_noccmp1:
601601
; CHECK-SD: ; %bb.0:
602602
; CHECK-SD-NEXT: cmp x0, #0
603-
; CHECK-SD-NEXT: ccmp x0, #13, #4, lt
603+
; CHECK-SD-NEXT: ccmp x0, #13, #4, mi
604604
; CHECK-SD-NEXT: cset w8, gt
605605
; CHECK-SD-NEXT: cmp x2, #2
606606
; CHECK-SD-NEXT: ccmp x2, #4, #4, lt
@@ -630,7 +630,7 @@ define i64 @select_noccmp2(i64 %v1, i64 %v2, i64 %v3, i64 %r) {
630630
; CHECK-SD-LABEL: select_noccmp2:
631631
; CHECK-SD: ; %bb.0:
632632
; CHECK-SD-NEXT: cmp x0, #0
633-
; CHECK-SD-NEXT: ccmp x0, #13, #0, ge
633+
; CHECK-SD-NEXT: ccmp x0, #13, #0, pl
634634
; CHECK-SD-NEXT: cset w8, gt
635635
; CHECK-SD-NEXT: cmp w8, #0
636636
; CHECK-SD-NEXT: csel x0, xzr, x3, ne
@@ -664,7 +664,7 @@ define i32 @select_noccmp3(i32 %v0, i32 %v1, i32 %v2) {
664664
; CHECK-SD-LABEL: select_noccmp3:
665665
; CHECK-SD: ; %bb.0:
666666
; CHECK-SD-NEXT: cmp w0, #0
667-
; CHECK-SD-NEXT: ccmp w0, #13, #0, ge
667+
; CHECK-SD-NEXT: ccmp w0, #13, #0, pl
668668
; CHECK-SD-NEXT: cset w8, gt
669669
; CHECK-SD-NEXT: cmp w0, #22
670670
; CHECK-SD-NEXT: mov w9, #44 ; =0x2c
@@ -937,11 +937,11 @@ define i32 @f128_select_and_olt_oge(fp128 %v0, fp128 %v1, fp128 %v2, fp128 %v3,
937937
; CHECK-SD-NEXT: stp q2, q3, [sp] ; 32-byte Folded Spill
938938
; CHECK-SD-NEXT: bl ___lttf2
939939
; CHECK-SD-NEXT: cmp w0, #0
940-
; CHECK-SD-NEXT: cset w21, lt
940+
; CHECK-SD-NEXT: cset w21, mi
941941
; CHECK-SD-NEXT: ldp q0, q1, [sp] ; 32-byte Folded Reload
942942
; CHECK-SD-NEXT: bl ___getf2
943943
; CHECK-SD-NEXT: cmp w0, #0
944-
; CHECK-SD-NEXT: cset w8, ge
944+
; CHECK-SD-NEXT: cset w8, pl
945945
; CHECK-SD-NEXT: tst w8, w21
946946
; CHECK-SD-NEXT: csel w0, w20, w19, ne
947947
; CHECK-SD-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload
@@ -964,8 +964,8 @@ define i32 @f128_select_and_olt_oge(fp128 %v0, fp128 %v1, fp128 %v2, fp128 %v3,
964964
; CHECK-GI-NEXT: ldp q1, q0, [sp] ; 32-byte Folded Reload
965965
; CHECK-GI-NEXT: bl ___getf2
966966
; CHECK-GI-NEXT: cmp w21, #0
967-
; CHECK-GI-NEXT: ccmp w0, #0, #8, lt
968-
; CHECK-GI-NEXT: csel w0, w19, w20, ge
967+
; CHECK-GI-NEXT: ccmp w0, #0, #8, mi
968+
; CHECK-GI-NEXT: csel w0, w19, w20, pl
969969
; CHECK-GI-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload
970970
; CHECK-GI-NEXT: ldp x20, x19, [sp, #48] ; 16-byte Folded Reload
971971
; CHECK-GI-NEXT: ldp x22, x21, [sp, #32] ; 16-byte Folded Reload

‎llvm/test/CodeGen/AArch64/arm64-fmax.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ define i64 @test_integer(i64 %in) {
6060
; CHECK-LABEL: test_integer:
6161
; CHECK: // %bb.0:
6262
; CHECK-NEXT: cmp x0, #0
63-
; CHECK-NEXT: csel x0, xzr, x0, lt
63+
; CHECK-NEXT: csel x0, xzr, x0, mi
6464
; CHECK-NEXT: ret
6565
%cmp = icmp slt i64 %in, 0
6666
%val = select i1 %cmp, i64 0, i64 %in

‎llvm/test/CodeGen/AArch64/arm64-fp128.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -258,7 +258,7 @@ define i32 @test_br_cc(fp128 %lhs, fp128 %rhs) {
258258
; CHECK-SD-NEXT: mov w8, #29 // =0x1d
259259
; CHECK-SD-NEXT: cmp w0, #0
260260
; CHECK-SD-NEXT: mov w9, #42 // =0x2a
261-
; CHECK-SD-NEXT: csel w0, w9, w8, lt
261+
; CHECK-SD-NEXT: csel w0, w9, w8, mi
262262
; CHECK-SD-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
263263
; CHECK-SD-NEXT: ret
264264
;
@@ -271,7 +271,7 @@ define i32 @test_br_cc(fp128 %lhs, fp128 %rhs) {
271271
; CHECK-GI-NEXT: mov w8, #29 // =0x1d
272272
; CHECK-GI-NEXT: mov w9, #42 // =0x2a
273273
; CHECK-GI-NEXT: cmp w0, #0
274-
; CHECK-GI-NEXT: csel w0, w9, w8, lt
274+
; CHECK-GI-NEXT: csel w0, w9, w8, mi
275275
; CHECK-GI-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
276276
; CHECK-GI-NEXT: ret
277277
%cond = fcmp olt fp128 %lhs, %rhs

‎llvm/test/CodeGen/AArch64/arm64-vabs.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1888,10 +1888,10 @@ define <2 x i128> @uabd_i64(<2 x i64> %a, <2 x i64> %b) {
18881888
; CHECK-GI-NEXT: subs x10, x11, x13
18891889
; CHECK-GI-NEXT: sbc x11, x14, x15
18901890
; CHECK-GI-NEXT: cmp x9, #0
1891-
; CHECK-GI-NEXT: cset w12, lt
1891+
; CHECK-GI-NEXT: cset w12, mi
18921892
; CHECK-GI-NEXT: csel w12, wzr, w12, eq
18931893
; CHECK-GI-NEXT: cmp x11, #0
1894-
; CHECK-GI-NEXT: cset w13, lt
1894+
; CHECK-GI-NEXT: cset w13, mi
18951895
; CHECK-GI-NEXT: csel w13, wzr, w13, eq
18961896
; CHECK-GI-NEXT: negs x14, x8
18971897
; CHECK-GI-NEXT: ngc x15, x9

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