Skip to content

Commit e6f3cca

Browse files
[RISCV] Update SpacemiT-X60 vector mask instructions latencies (#150644)
This PR adds hardware-measured latencies for all instructions defined in Section 15 of the RVV specification: "Vector Mask Instructions" to the SpacemiT-X60 scheduling model.
1 parent d69320e commit e6f3cca

File tree

3 files changed

+435
-424
lines changed

3 files changed

+435
-424
lines changed

llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td

Lines changed: 17 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -756,13 +756,24 @@ foreach mx = SchedMxListFWRed in {
756756
foreach mx = SchedMxList in {
757757
defvar IsWorstCase = SMX60IsWorstCaseMX<mx, SchedMxList>.c;
758758

759-
defm "" : LMULWriteResMX<"WriteVMALUV", [SMX60_VIEU], mx, IsWorstCase>;
760-
defm "" : LMULWriteResMX<"WriteVMPopV", [SMX60_VIEU], mx, IsWorstCase>;
761-
defm "" : LMULWriteResMX<"WriteVMFFSV", [SMX60_VIEU], mx, IsWorstCase>;
762-
defm "" : LMULWriteResMX<"WriteVMSFSV", [SMX60_VIEU], mx, IsWorstCase>;
759+
let Latency = 4 in {
760+
defm "" : LMULWriteResMX<"WriteVMALUV", [SMX60_VIEU], mx, IsWorstCase>;
761+
}
762+
let Latency = 4, ReleaseAtCycles = [ConstValueUntilLMULThenDouble<"M2", 1, mx>.c] in {
763+
defm "" : LMULWriteResMX<"WriteVMSFSV", [SMX60_VIEU], mx, IsWorstCase>;
764+
}
763765

764-
defm "" : LMULWriteResMX<"WriteVIotaV", [SMX60_VIEU], mx, IsWorstCase>;
765-
defm "" : LMULWriteResMX<"WriteVIdxV", [SMX60_VIEU], mx, IsWorstCase>;
766+
let Latency = 6, ReleaseAtCycles = [2] in {
767+
defm "" : LMULWriteResMX<"WriteVMPopV", [SMX60_VIEU], mx, IsWorstCase>;
768+
defm "" : LMULWriteResMX<"WriteVMFFSV", [SMX60_VIEU], mx, IsWorstCase>;
769+
}
770+
771+
defvar VIotaLat = ConstValueUntilLMULThenDouble<"M2", 4, mx>.c;
772+
defvar VIotaOcc = ConstOneUntilMF2ThenDouble<mx>.c;
773+
let Latency = VIotaLat, ReleaseAtCycles = [VIotaOcc] in {
774+
defm "" : LMULWriteResMX<"WriteVIotaV", [SMX60_VIEU], mx, IsWorstCase>;
775+
defm "" : LMULWriteResMX<"WriteVIdxV", [SMX60_VIEU], mx, IsWorstCase>;
776+
}
766777
}
767778

768779
// 16. Vector Permutation Instructions

0 commit comments

Comments
 (0)