[Sparc] Optimize compare instruction (#167140)

koachan · doac · web-flow · commit e6f868cf7178 · 2025-11-14T23:11:38.000+07:00
If we need to compare the result of a computation with 0, we can
sometimes replace the last instruction in the computation with one that
sets the integer condition codes. We can then branch immediately based
on the zero-flag instead of having to use an extra compare instruction
(a SUBcc instruction).

This is only possible if the result of the compare is not used anywhere
else and that no other instruction modifies the integer condition codes
between the time the result of the computation is defined and the time
it is used.

---------

Co-authored-by: Daniel Cederman &lt;cederman@gaisler.com&gt;
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -641,6 +641,145 @@ unsigned SparcInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   return get(Opcode).getSize();
 }
 
+bool SparcInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
+                                    Register &SrcReg2, int64_t &CmpMask,
+                                    int64_t &CmpValue) const {
+  Register DstReg;
+  switch (MI.getOpcode()) {
+  default:
+    break;
+  case SP::SUBCCri:
+    DstReg = MI.getOperand(0).getReg();
+    SrcReg = MI.getOperand(1).getReg();
+    SrcReg2 = 0;
+    CmpMask = ~0;
+    CmpValue = MI.getOperand(2).getImm();
+    return DstReg == SP::G0 && CmpValue == 0;
+  case SP::SUBCCrr:
+    DstReg = MI.getOperand(0).getReg();
+    SrcReg = MI.getOperand(1).getReg();
+    SrcReg2 = MI.getOperand(2).getReg();
+    CmpMask = ~0;
+    CmpValue = 0;
+    return DstReg == SP::G0 && SrcReg2 == SP::G0;
+  }
+
+  return false;
+}
+
+bool SparcInstrInfo::optimizeCompareInstr(
+    MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask,
+    int64_t CmpValue, const MachineRegisterInfo *MRI) const {
+
+  // Get the unique definition of SrcReg.
+  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
+  if (!MI)
+    return false;
+
+  // Only optimize if defining and comparing instruction in same block.
+  if (MI->getParent() != CmpInstr.getParent())
+    return false;
+
+  unsigned NewOpcode;
+  switch (MI->getOpcode()) {
+  case SP::ANDNrr:
+    NewOpcode = SP::ANDNCCrr;
+    break;
+  case SP::ANDNri:
+    NewOpcode = SP::ANDNCCri;
+    break;
+  case SP::ANDrr:
+    NewOpcode = SP::ANDCCrr;
+    break;
+  case SP::ANDri:
+    NewOpcode = SP::ANDCCri;
+    break;
+  case SP::ORrr:
+    NewOpcode = SP::ORCCrr;
+    break;
+  case SP::ORri:
+    NewOpcode = SP::ORCCri;
+    break;
+  case SP::ORNCCrr:
+    NewOpcode = SP::ORNCCrr;
+    break;
+  case SP::ORNri:
+    NewOpcode = SP::ORNCCri;
+    break;
+  case SP::XORrr:
+    NewOpcode = SP::XORCCrr;
+    break;
+  case SP::XNORri:
+    NewOpcode = SP::XNORCCri;
+    break;
+  case SP::XNORrr:
+    NewOpcode = SP::XNORCCrr;
+    break;
+  case SP::ADDrr:
+    NewOpcode = SP::ADDCCrr;
+    break;
+  case SP::ADDri:
+    NewOpcode = SP::ADDCCri;
+    break;
+  case SP::SUBrr:
+    NewOpcode = SP::SUBCCrr;
+    break;
+  case SP::SUBri:
+    NewOpcode = SP::SUBCCri;
+    break;
+  default:
+    return false;
+  }
+
+  bool IsICCModified = false;
+  MachineBasicBlock::iterator I = MI;
+  MachineBasicBlock::iterator C = CmpInstr;
+  MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
+  const TargetRegisterInfo *TRI = &getRegisterInfo();
+
+  // If ICC is used or modified between MI and CmpInstr we cannot optimize.
+  while (++I != C) {
+    if (I->modifiesRegister(SP::ICC, TRI) || I->readsRegister(SP::ICC, TRI))
+      return false;
+  }
+
+  while (++I != E) {
+    // Only allow conditionals on equality.
+    if (I->readsRegister(SP::ICC, TRI)) {
+      bool IsICCBranch = I->getOpcode() == SP::BCOND ||
+                         I->getOpcode() == SP::BPICC ||
+                         I->getOpcode() == SP::BPXCC;
+      bool IsICCMove =
+          I->getOpcode() == SP::MOVICCrr || I->getOpcode() == SP::MOVICCri ||
+          I->getOpcode() == SP::MOVXCCrr || I->getOpcode() == SP::MOVXCCri;
+      bool IsICCConditional = IsICCBranch || IsICCMove;
+      if (!IsICCConditional ||
+          (I->getOperand(IsICCBranch ? 1 : 3).getImm() != SPCC::ICC_E &&
+           I->getOperand(IsICCBranch ? 1 : 3).getImm() != SPCC::ICC_NE))
+        return false;
+    } else if (I->modifiesRegister(SP::ICC, TRI)) {
+      IsICCModified = true;
+      break;
+    }
+  }
+
+  if (!IsICCModified) {
+    MachineBasicBlock *MBB = CmpInstr.getParent();
+    if (any_of(MBB->successors(),
+               [](MachineBasicBlock *Succ) { return Succ->isLiveIn(SP::ICC); }))
+      return false;
+  }
+
+  if (MRI->hasOneNonDBGUse(SrcReg))
+    MI->getOperand(0).setReg(SP::G0);
+
+  MI->setDesc(get(NewOpcode));
+  MI->addRegisterDefined(SP::ICC);
+  CmpInstr.eraseFromParent();
+
+  return true;
+}
+
 bool SparcInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
   switch (MI.getOpcode()) {
   case TargetOpcode::LOAD_STACK_GUARD: {
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.h b/llvm/lib/Target/Sparc/SparcInstrInfo.h
@@ -107,6 +107,14 @@ class SparcInstrInfo : public SparcGenInstrInfo {
   /// instruction may be.  This returns the maximum number of bytes.
   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
 
+  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
+                      Register &SrcReg2, int64_t &CmpMask,
+                      int64_t &CmpValue) const override;
+
+  bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
+                            Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
+                            const MachineRegisterInfo *MRI) const override;
+
   // Lower pseudo instructions after register allocation.
   bool expandPostRAPseudo(MachineInstr &MI) const override;
 };
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -908,7 +908,7 @@ defm SUB    : F3_12  <"sub"  , 0b000100, sub, IntRegs, i32, simm13Op>;
 let Uses = [ICC], Defs = [ICC] in
   defm SUBE   : F3_12  <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
 
-let Defs = [ICC], hasPostISelHook = true in
+let Defs = [ICC], hasPostISelHook = true, isCompare = 1 in
   defm SUBCC  : F3_12  <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
 
 let Uses = [ICC] in
diff --git a/llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll
@@ -292,17 +292,15 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) {
 ; CHECK-NEXT:    mov %g0, %l0
 ; CHECK-NEXT:    addcc %g3, -1, %o3
 ; CHECK-NEXT:    addxcc %g2, -1, %o2
-; CHECK-NEXT:    or %g3, %g2, %l1
-; CHECK-NEXT:    cmp %l1, 0
+; CHECK-NEXT:    orcc %g3, %g2, %g0
 ; CHECK-NEXT:    move %icc, 1, %i5
 ; CHECK-NEXT:    cmp %g2, %i1
 ; CHECK-NEXT:    movgu %icc, 1, %g4
 ; CHECK-NEXT:    cmp %g3, %i2
 ; CHECK-NEXT:    movgu %icc, 1, %l0
 ; CHECK-NEXT:    cmp %g2, %i1
 ; CHECK-NEXT:    move %icc, %l0, %g4
-; CHECK-NEXT:    or %i5, %g4, %i5
-; CHECK-NEXT:    cmp %i5, 0
+; CHECK-NEXT:    orcc %i5, %g4, %g0
 ; CHECK-NEXT:    movne %icc, %i1, %o2
 ; CHECK-NEXT:    movne %icc, %i2, %o3
 ; CHECK-NEXT:    std %g2, [%fp+-8]
diff --git a/llvm/test/CodeGen/SPARC/ctlz.ll b/llvm/test/CodeGen/SPARC/ctlz.ll
@@ -156,8 +156,7 @@ define i64 @i64_nopoison(i64 %x) nounwind {
 ; SPARC-LABEL: i64_nopoison:
 ; SPARC:       ! %bb.0:
 ; SPARC-NEXT:    save %sp, -96, %sp
-; SPARC-NEXT:    or %i1, %i0, %i2
-; SPARC-NEXT:    cmp %i2, 0
+; SPARC-NEXT:    orcc %i1, %i0, %g0
 ; SPARC-NEXT:    be .LBB2_4
 ; SPARC-NEXT:    nop
 ; SPARC-NEXT:  ! %bb.1: ! %cond.false
@@ -182,8 +181,7 @@ define i64 @i64_nopoison(i64 %x) nounwind {
 ; SPARC-POPC-LABEL: i64_nopoison:
 ; SPARC-POPC:       ! %bb.0:
 ; SPARC-POPC-NEXT:    save %sp, -96, %sp
-; SPARC-POPC-NEXT:    or %i1, %i0, %i2
-; SPARC-POPC-NEXT:    cmp %i2, 0
+; SPARC-POPC-NEXT:    orcc %i1, %i0, %g0
 ; SPARC-POPC-NEXT:    be .LBB2_4
 ; SPARC-POPC-NEXT:    nop
 ; SPARC-POPC-NEXT:  ! %bb.1: ! %cond.false
diff --git a/llvm/test/CodeGen/SPARC/cttz.ll b/llvm/test/CodeGen/SPARC/cttz.ll
@@ -184,8 +184,7 @@ define i32 @i32_poison(i32 %x) nounwind {
 define i64 @i64_nopoison(i64 %x) nounwind {
 ; SPARC-LABEL: i64_nopoison:
 ; SPARC:       ! %bb.0:
-; SPARC-NEXT:    or %o1, %o0, %o2
-; SPARC-NEXT:    cmp %o2, 0
+; SPARC-NEXT:    orcc %o1, %o0, %g0
 ; SPARC-NEXT:    be .LBB2_3
 ; SPARC-NEXT:    nop
 ; SPARC-NEXT:  ! %bb.1: ! %cond.false
@@ -219,8 +218,7 @@ define i64 @i64_nopoison(i64 %x) nounwind {
 ;
 ; SPARC-POPC-LABEL: i64_nopoison:
 ; SPARC-POPC:       ! %bb.0:
-; SPARC-POPC-NEXT:    or %o1, %o0, %o2
-; SPARC-POPC-NEXT:    cmp %o2, 0
+; SPARC-POPC-NEXT:    orcc %o1, %o0, %g0
 ; SPARC-POPC-NEXT:    be .LBB2_3
 ; SPARC-POPC-NEXT:    nop
 ; SPARC-POPC-NEXT:  ! %bb.1: ! %cond.false
diff --git a/llvm/test/CodeGen/SPARC/fp128-select.ll b/llvm/test/CodeGen/SPARC/fp128-select.ll
@@ -22,8 +22,7 @@ define fp128 @f128_select_soft(fp128 %a, fp128 %b) #0 {
 ; V9-NEXT:    sllx %o3, 32, %o3
 ; V9-NEXT:    or %o3, %o2, %o2
 ; V9-NEXT:    xor %o1, %o2, %o1
-; V9-NEXT:    or %o0, %o1, %o0
-; V9-NEXT:    cmp %o0, 0
+; V9-NEXT:    orcc %o0, %o1, %g0
 ; V9-NEXT:    bne %xcc, .LBB0_2
 ; V9-NEXT:    nop
 ; V9-NEXT:  ! %bb.1:
diff --git a/llvm/test/CodeGen/SPARC/optcompare.ll b/llvm/test/CodeGen/SPARC/optcompare.ll
diff --git a/llvm/test/CodeGen/SPARC/smulo-128-legalisation-lowering.ll b/llvm/test/CodeGen/SPARC/smulo-128-legalisation-lowering.ll
diff --git a/llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll b/llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll
