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[Hexagon] Enable FMINUMUM/FMAXIMUMNUM to have same behavior as FMINNUM/FMAXNUM
1 parent b42c883 commit e7467be

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6 files changed

+37
-12
lines changed

6 files changed

+37
-12
lines changed

‎llvm/lib/Target/Hexagon/HexagonISelLowering.cpp‎

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1493,9 +1493,9 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
14931493
// - indexed loads and stores (pre-/post-incremented),
14941494
// - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
14951495
// ConstantFP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1496-
// FLOG, FLOG2, FLOG10, FMAXIMUMNUM, FMINIMUMNUM, FNEARBYINT, FRINT, FROUND,
1497-
// TRAP, FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG,
1498-
// ZERO_EXTEND_VECTOR_INREG,
1496+
// FLOG, FLOG2, FLOG10, FMAXIMUMNUM, FMAXNUM, FMINIMUMNUM, FMINNUM
1497+
// FNEARBYINT, FRINT, FROUND, TRAP, FTRUNC, PREFETCH,
1498+
// SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
14991499
// which default to "expand" for at least one type.
15001500

15011501
// Misc operations.
@@ -1648,7 +1648,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
16481648
ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2,
16491649
ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
16501650
ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
1651-
ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM,
1651+
ISD::FMINIMUMNUM, ISD::FMINNUM, ISD::FMAXIMUMNUM, ISD::FMAXNUM,
16521652
ISD::FSINCOS, ISD::FLDEXP,
16531653
// Misc:
16541654
ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool,
@@ -1783,7 +1783,9 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
17831783
setOperationAction(ISD::FDIV, MVT::f32, Custom);
17841784

17851785
setOperationAction(ISD::FMINIMUMNUM, MVT::f32, Legal);
1786+
setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
17861787
setOperationAction(ISD::FMAXIMUMNUM, MVT::f32, Legal);
1788+
setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
17871789

17881790
setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
17891791
setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
@@ -1832,7 +1834,9 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
18321834
}
18331835
if (Subtarget.hasV67Ops()) {
18341836
setOperationAction(ISD::FMINIMUMNUM, MVT::f64, Legal);
1837+
setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
18351838
setOperationAction(ISD::FMAXIMUMNUM, MVT::f64, Legal);
1839+
setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
18361840
setOperationAction(ISD::FMUL, MVT::f64, Legal);
18371841
}
18381842

‎llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -128,7 +128,9 @@ HexagonTargetLowering::initializeHVXLowering() {
128128
setOperationAction(ISD::FSUB, T, Legal);
129129
setOperationAction(ISD::FMUL, T, Legal);
130130
setOperationAction(ISD::FMINIMUMNUM, T, Legal);
131+
setOperationAction(ISD::FMINNUM, T, Legal);
131132
setOperationAction(ISD::FMAXIMUMNUM, T, Legal);
133+
setOperationAction(ISD::FMAXNUM, T, Legal);
132134

133135
setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom);
134136
setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom);
@@ -165,7 +167,9 @@ HexagonTargetLowering::initializeHVXLowering() {
165167
setOperationAction(ISD::FSUB, P, Custom);
166168
setOperationAction(ISD::FMUL, P, Custom);
167169
setOperationAction(ISD::FMINIMUMNUM, P, Custom);
170+
setOperationAction(ISD::FMINNUM, P, Custom);
168171
setOperationAction(ISD::FMAXIMUMNUM, P, Custom);
172+
setOperationAction(ISD::FMAXNUM, P, Custom);
169173
setOperationAction(ISD::SETCC, P, Custom);
170174
setOperationAction(ISD::VSELECT, P, Custom);
171175

@@ -3173,7 +3177,9 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const {
31733177
case ISD::FSUB:
31743178
case ISD::FMUL:
31753179
case ISD::FMINIMUMNUM:
3180+
case ISD::FMINNUM:
31763181
case ISD::FMAXIMUMNUM:
3182+
case ISD::FMAXNUM:
31773183
case ISD::MULHS:
31783184
case ISD::MULHU:
31793185
case ISD::AND:

‎llvm/lib/Target/Hexagon/HexagonPatterns.td‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1580,7 +1580,9 @@ def: OpR_RR_pat<F2_sfadd, pf2<fadd>, f32, F32>;
15801580
def: OpR_RR_pat<F2_sfsub, pf2<fsub>, f32, F32>;
15811581
def: OpR_RR_pat<F2_sfmpy, pf2<fmul>, f32, F32>;
15821582
def: OpR_RR_pat<F2_sfmin, pf2<fminimumnum>, f32, F32>;
1583+
def: OpR_RR_pat<F2_sfmin, pf2<fminnum>, f32, F32>;
15831584
def: OpR_RR_pat<F2_sfmax, pf2<fmaximumnum>, f32, F32>;
1585+
def: OpR_RR_pat<F2_sfmax, pf2<fmaxnum>, f32, F32>;
15841586

15851587
let Predicates = [HasV66] in {
15861588
def: OpR_RR_pat<F2_dfadd, pf2<fadd>, f64, F64>;
@@ -1601,7 +1603,9 @@ let Predicates = [HasV67,UseUnsafeMath], AddedComplexity = 50 in {
16011603
}
16021604
let Predicates = [HasV67] in {
16031605
def: OpR_RR_pat<F2_dfmin, pf2<fminimumnum>, f64, F64>;
1606+
def: OpR_RR_pat<F2_dfmin, pf2<fminnum>, f64, F64>;
16041607
def: OpR_RR_pat<F2_dfmax, pf2<fmaximumnum>, f64, F64>;
1608+
def: OpR_RR_pat<F2_dfmax, pf2<fmaxnum>, f64, F64>;
16051609

16061610
def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy (F2_dfmpyfix $Rs, $Rt),
16071611
(F2_dfmpyfix $Rt, $Rs))>;

‎llvm/lib/Target/Hexagon/HexagonPatternsHVX.td‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -512,6 +512,12 @@ let Predicates = [UseHVXV68, UseHVX128B, UseHVXQFloat] in {
512512
def: OpR_RR_pat<V6_vmax_hf, pf2<fmaximumnum>, VecF16, HVF16>;
513513
def: OpR_RR_pat<V6_vmin_sf, pf2<fminimumnum>, VecF32, HVF32>;
514514
def: OpR_RR_pat<V6_vmax_sf, pf2<fmaximumnum>, VecF32, HVF32>;
515+
516+
def: OpR_RR_pat<V6_vmin_hf, pf2<fminnum>, VecF16, HVF16>;
517+
def: OpR_RR_pat<V6_vmax_hf, pf2<fmaxnum>, VecF16, HVF16>;
518+
def: OpR_RR_pat<V6_vmin_sf, pf2<fminnum>, VecF32, HVF32>;
519+
def: OpR_RR_pat<V6_vmax_sf, pf2<fmaxnum>, VecF32, HVF32>;
520+
515521
}
516522

517523
let Predicates = [UseHVXV68, UseHVX128B, UseHVXIEEEFP] in {
@@ -525,6 +531,11 @@ let Predicates = [UseHVXV68, UseHVX128B, UseHVXIEEEFP] in {
525531
def: OpR_RR_pat<V6_vfmax_hf, pf2<fmaximumnum>, VecF16, HVF16>;
526532
def: OpR_RR_pat<V6_vfmin_sf, pf2<fminimumnum>, VecF32, HVF32>;
527533
def: OpR_RR_pat<V6_vfmax_sf, pf2<fmaximumnum>, VecF32, HVF32>;
534+
535+
def: OpR_RR_pat<V6_vfmin_hf, pf2<fminnum>, VecF16, HVF16>;
536+
def: OpR_RR_pat<V6_vfmax_hf, pf2<fmaxnum>, VecF16, HVF16>;
537+
def: OpR_RR_pat<V6_vfmin_sf, pf2<fminnum>, VecF32, HVF32>;
538+
def: OpR_RR_pat<V6_vfmax_sf, pf2<fmaxnum>, VecF32, HVF32>;
528539
}
529540

530541
let Predicates = [UseHVX] in {

‎llvm/test/CodeGen/Hexagon/fminmax-v67.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22

33

44
; CHECK-LABEL: t1
5-
; CHECK: call fmax
5+
; CHECK: dfmax
66

77
define dso_local double @t1(double %a, double %b) local_unnamed_addr {
88
entry:
@@ -11,7 +11,7 @@ entry:
1111
}
1212

1313
; CHECK-LABEL: t2
14-
; CHECK: call fmin
14+
; CHECK: dfmin
1515

1616
define dso_local double @t2(double %a, double %b) local_unnamed_addr {
1717
entry:
@@ -20,7 +20,7 @@ entry:
2020
}
2121

2222
; CHECK-LABEL: t3
23-
; CHECK: call fmaxf
23+
; CHECK: sfmax
2424

2525
define dso_local float @t3(float %a, float %b) local_unnamed_addr {
2626
entry:
@@ -29,7 +29,7 @@ entry:
2929
}
3030

3131
; CHECK-LABEL: t4
32-
; CHECK: call fminf
32+
; CHECK: sfmin
3333

3434
define dso_local float @t4(float %a, float %b) local_unnamed_addr {
3535
entry:

‎llvm/test/CodeGen/Hexagon/fminmax.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,31 +4,31 @@ target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i
44
target triple = "hexagon"
55

66
; CHECK-LABEL: cfminf
7-
; CHECK: call fminf
7+
; CHECK: sfmin
88
define float @cfminf(float %x, float %y) #0 {
99
entry:
1010
%call = tail call float @fminf(float %x, float %y) #1
1111
ret float %call
1212
}
1313

1414
; CHECK-LABEL: cfmaxf
15-
; CHECK: call fmaxf
15+
; CHECK: sfmax
1616
define float @cfmaxf(float %x, float %y) #0 {
1717
entry:
1818
%call = tail call float @fmaxf(float %x, float %y) #1
1919
ret float %call
2020
}
2121

2222
; CHECK-LABEL: minnum
23-
; CHECK: call fminf
23+
; CHECK: sfmin
2424
define float @minnum(float %x, float %y) #0 {
2525
entry:
2626
%call = tail call float @llvm.minnum.f32(float %x, float %y) #1
2727
ret float %call
2828
}
2929

3030
; CHECK-LABEL: maxnum
31-
; CHECK: call fmaxf
31+
; CHECK: sfmax
3232
define float @maxnum(float %x, float %y) #0 {
3333
entry:
3434
%call = tail call float @llvm.maxnum.f32(float %x, float %y) #1

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