Skip to content

Commit e790c97

Browse files
futogfutog
authored
[RISCV] Make "target-feature +i" explicit (#157835)
Add "target-feature +i" for RV32I/RV64I. Current behavior: RV32E/RV64E: "target-feature +e" "target-feature -i" RV32I/RV64I: "target-feature -e" Adding "target-feature +i" explicitly makes the behavior consistent.
1 parent bf6debc commit e790c97

File tree

8 files changed

+42
-30
lines changed

8 files changed

+42
-30
lines changed

‎clang/test/CodeGen/RISCV/riscv-func-attr-target.c‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -80,16 +80,16 @@ int test_vsetvlmax_e64m1() {
8080
}
8181

8282
//.
83-
// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zifencei,+zmmul,-relax,-zbb,-zfa" }
84-
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }
85-
// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa" }
86-
// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }
83+
// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+i,+m,+save-restore,+zaamo,+zalrsc,+zifencei,+zmmul,-relax,-zbb,-zfa" }
84+
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+i,+m,+save-restore,+v,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }
85+
// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+i,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa" }
86+
// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+i,+m,+save-restore,+v,+zaamo,+zalrsc,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }
8787
// Make sure we append negative features if we override the arch
88-
// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zca,+zcd,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
89-
// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
90-
// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa" }
91-
// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
92-
// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
93-
// CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
94-
// CHECK: attributes #11 = { {{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
95-
// CHECK: attributes #12 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa" }
88+
// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+i,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zca,+zcd,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
89+
// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+i,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
90+
// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+i,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa" }
91+
// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+i,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
92+
// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+save-restore,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
93+
// CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+i,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
94+
// CHECK: attributes #11 = { {{.*}}"target-features"="+64bit,+a,+f,+i,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
95+
// CHECK: attributes #12 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+i,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa" }

‎clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,10 +21,10 @@ unsigned long test_vlenb(void) {
2121
return __riscv_vlenb();
2222
}
2323
//.
24-
// RV32: attributes #[[ATTR0:[0-9]+]] = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
24+
// RV32: attributes #[[ATTR0:[0-9]+]] = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
2525
// RV32: attributes #[[ATTR1:[0-9]+]] = { mustprogress nocallback nofree nosync nounwind willreturn memory(read) }
2626
//.
27-
// RV64: attributes #[[ATTR0:[0-9]+]] = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
27+
// RV64: attributes #[[ATTR0:[0-9]+]] = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
2828
// RV64: attributes #[[ATTR1:[0-9]+]] = { mustprogress nocallback nofree nosync nounwind willreturn memory(read) }
2929
//.
3030
// RV32: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}

‎clang/test/Driver/riscv-cpus.c‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -401,12 +401,16 @@
401401

402402
// -march overwrite -mcpu's default -march
403403
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -march=rv32imc | FileCheck -check-prefix=MCPU-MARCH %s
404-
// MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" "+m" "-target-feature" "+c"
404+
// MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31"
405+
// MCPU-MARCH: "-target-feature" "+m" "-target-feature" "+c"
405406
// MCPU-MARCH: "-target-abi" "ilp32"
406407

407408
// -march=unset erases previous march
408409
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -march=rv32imc -march=unset -mcpu=sifive-e31 | FileCheck -check-prefix=MARCH-UNSET %s
409-
// MARCH-UNSET: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+c"
410+
// MARCH-UNSET: "-nostdsysteminc" "-target-cpu" "sifive-e31"
411+
// MARCH-UNSET: "-target-feature" "+m"
412+
// MARCH-UNSET: "-target-feature" "+a"
413+
// MARCH-UNSET: "-target-feature" "+c"
410414
// MARCH-UNSET-SAME: "-target-abi" "ilp32"
411415

412416
// Check interaction between -mcpu and mtune, -mtune won't affect arch related

‎clang/test/Driver/riscv-default-features.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// RUN: %clang --target=riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32
22
// RUN: %clang --target=riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64
33

4-
// RV32: "target-features"="+32bit,+a,+c,+m,+relax,
5-
// RV64: "target-features"="+64bit,+a,+c,+m,+relax,
4+
// RV32: "target-features"="+32bit,+a,+c,+i,+m,+relax,
5+
// RV64: "target-features"="+64bit,+a,+c,+i,+m,+relax,
66

77
// Dummy function
88
int foo(void){

‎clang/test/Driver/riscv-features.c‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
12
// RUN: %clang --target=riscv32-unknown-elf -### %s -fsyntax-only 2>&1 | FileCheck %s
23
// RUN: %clang --target=riscv64-unknown-elf -### %s -fsyntax-only 2>&1 | FileCheck %s
34
// RUN: %clang --target=riscv64-linux-android -### %s -fsyntax-only 2>&1 | FileCheck %s -check-prefixes=ANDROID,DEFAULT,FAST-SCALAR-UNALIGNED-ACCESS,FAST-VECTOR-UNALIGNED-ACCESS
@@ -85,3 +86,14 @@
8586
// FUCHSIA-SAME: "-target-feature" "+zbb"
8687
// FUCHSIA-SAME: "-target-feature" "+zbs"
8788

89+
90+
// RUN: %clang --target=riscv32-unknown-elf -### -march=rv32i %s -fsyntax-only 2>&1 | FileCheck %s -check-prefix=RVI
91+
// RUN: %clang --target=riscv32-unknown-elf -### -march=rv64i %s -fsyntax-only 2>&1 | FileCheck %s -check-prefix=RVI
92+
// RUN: %clang --target=riscv32-unknown-elf -### -march=rv32e %s -fsyntax-only 2>&1 | FileCheck %s -check-prefix=RVE
93+
// RUN: %clang --target=riscv32-unknown-elf -### -march=rv64e %s -fsyntax-only 2>&1 | FileCheck %s -check-prefix=RVE
94+
95+
// RVI: "-target-feature" "+i"
96+
// RVI-SAME: "-target-feature" "-e"
97+
98+
// RVE: "-target-feature" "+e"
99+
// RVE-SAME: "-target-feature" "-i"

‎flang/test/Driver/target-cpu-features.f90‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@
7474
! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" "-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" "-target-feature" "-fsgsbase"
7575

7676
! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
77-
! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c"
77+
! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+i" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c"
7878

7979
! CHECK-AMDGPU: "-fc1" "-triple" "amdgcn-amd-amdhsa"
8080
! CHECK-AMDGPU-SAME: "-target-cpu" "gfx908"

‎llvm/lib/TargetParser/RISCVISAInfo.cpp‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -287,11 +287,6 @@ std::vector<std::string> RISCVISAInfo::toFeatures(bool AddAllExtensions,
287287
bool IgnoreUnknown) const {
288288
std::vector<std::string> Features;
289289
for (const auto &[ExtName, _] : Exts) {
290-
// i is a base instruction set, not an extension (see
291-
// https://github.com/riscv/riscv-isa-manual/blob/main/src/naming.adoc#base-integer-isa)
292-
// and is not recognized in clang -cc1
293-
if (ExtName == "i")
294-
continue;
295290
if (IgnoreUnknown && !isSupportedExtension(ExtName))
296291
continue;
297292

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -809,7 +809,7 @@ TEST(ToFeatures, IIsDroppedAndExperimentalExtensionsArePrefixed) {
809809
RISCVISAInfo::parseArchString("rv64im_zalasr", true, false);
810810
ASSERT_THAT_EXPECTED(MaybeISAInfo1, Succeeded());
811811
EXPECT_THAT((*MaybeISAInfo1)->toFeatures(),
812-
ElementsAre("+m", "+zmmul", "+experimental-zalasr"));
812+
ElementsAre("+i", "+m", "+zmmul", "+experimental-zalasr"));
813813

814814
auto MaybeISAInfo2 = RISCVISAInfo::parseArchString(
815815
"rv32e_zalasr_xventanacondops", true, false);
@@ -822,26 +822,27 @@ TEST(ToFeatures, UnsupportedExtensionsAreDropped) {
822822
auto MaybeISAInfo =
823823
RISCVISAInfo::parseNormalizedArchString("rv64i2p0_m2p0_xmadeup1p0");
824824
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
825-
EXPECT_THAT((*MaybeISAInfo)->toFeatures(), ElementsAre("+m"));
825+
EXPECT_THAT((*MaybeISAInfo)->toFeatures(), ElementsAre("+i", "+m"));
826826
}
827827

828828
TEST(ToFeatures, UnsupportedExtensionsAreKeptIfIgnoreUnknownIsFalse) {
829829
auto MaybeISAInfo =
830830
RISCVISAInfo::parseNormalizedArchString("rv64i2p0_m2p0_xmadeup1p0");
831831
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
832832
EXPECT_THAT((*MaybeISAInfo)->toFeatures(false, false),
833-
ElementsAre("+m", "+xmadeup"));
833+
ElementsAre("+i", "+m", "+xmadeup"));
834834
}
835835

836836
TEST(ToFeatures, AddAllExtensionsAddsNegativeExtensions) {
837837
auto MaybeISAInfo = RISCVISAInfo::parseNormalizedArchString("rv64i2p0_m2p0");
838838
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
839839

840840
auto Features = (*MaybeISAInfo)->toFeatures(true);
841-
EXPECT_GT(Features.size(), 1UL);
842-
EXPECT_EQ(Features.front(), "+m");
841+
EXPECT_GT(Features.size(), 2UL);
842+
EXPECT_EQ(Features[0], "+i");
843+
EXPECT_EQ(Features[1], "+m");
843844
// Every feature after should be a negative feature
844-
for (auto &NegativeExt : llvm::drop_begin(Features))
845+
for (auto &NegativeExt : llvm::drop_begin(Features, 2))
845846
EXPECT_TRUE(NegativeExt.substr(0, 1) == "-");
846847
}
847848

0 commit comments

Comments
 (0)