Formatting

Author: huntergr-arm

llvm/include/llvm/Target/TargetSelectionDAG.td

@@ -840,8 +840,8 @@ def vector_insert_subvec : SDNode<"ISD::INSERT_SUBVECTOR",
 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
 
-def find_last_active : SDNode<"ISD::VECTOR_FIND_LAST_ACTIVE",
-                              SDTypeProfile<1, 1, []>, []>;
+def find_last_active
+    : SDNode<"ISD::VECTOR_FIND_LAST_ACTIVE", SDTypeProfile<1, 1, []>, []>;
 
 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
 // these internally.  Don't reference these directly.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -19946,8 +19946,7 @@ performLastTrueTestVectorCombine(SDNode *N,
 }
 
 static SDValue
-performExtractLastActiveCombine(SDNode *N,
-                                TargetLowering::DAGCombinerInfo &DCI,
+performExtractLastActiveCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
                                 const AArch64Subtarget *Subtarget) {
   assert(N->getOpcode() == ISD::EXTRACT_VECTOR_ELT);
   SelectionDAG &DAG = DCI.DAG;
@@ -19960,12 +19959,12 @@ performExtractLastActiveCombine(SDNode *N,
 
   SDValue Mask = Idx.getOperand(0);
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
-  if (TLI.getOperationAction(ISD::VECTOR_FIND_LAST_ACTIVE, Mask.getValueType())
-      != TargetLowering::Legal)
+  if (TLI.getOperationAction(ISD::VECTOR_FIND_LAST_ACTIVE,
+                             Mask.getValueType()) != TargetLowering::Legal)
     return SDValue();
 
-  return DAG.getNode(AArch64ISD::LASTB, SDLoc(N), N->getValueType(0),
-                     Mask, Vec);
+  return DAG.getNode(AArch64ISD::LASTB, SDLoc(N), N->getValueType(0), Mask,
+                     Vec);
 }
 
 static SDValue

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

@@ -3381,14 +3381,17 @@ let Predicates = [HasSVE_or_SME] in {
 
   // Find index of last active lane. This is a fallback in case we miss the
   // opportunity to fold into a lastb or clastb directly.
-  def : Pat<(i64 (find_last_active nxv16i1:$P1)),
-            (INSERT_SUBREG (IMPLICIT_DEF), (LASTB_RPZ_B $P1, (INDEX_II_B 0, 1)), sub_32)>;
-  def : Pat<(i64 (find_last_active nxv8i1:$P1)),
-            (INSERT_SUBREG (IMPLICIT_DEF), (LASTB_RPZ_H $P1, (INDEX_II_H 0, 1)), sub_32)>;
-  def : Pat<(i64 (find_last_active nxv4i1:$P1)),
-            (INSERT_SUBREG (IMPLICIT_DEF), (LASTB_RPZ_S $P1, (INDEX_II_S 0, 1)), sub_32)>;
-  def : Pat<(i64 (find_last_active nxv2i1:$P1)),
-            (LASTB_RPZ_D $P1, (INDEX_II_D 0, 1))>;
+  def : Pat<(i64(find_last_active nxv16i1:$P1)),
+            (INSERT_SUBREG(IMPLICIT_DEF), (LASTB_RPZ_B $P1, (INDEX_II_B 0, 1)),
+                sub_32)>;
+  def : Pat<(i64(find_last_active nxv8i1:$P1)),
+            (INSERT_SUBREG(IMPLICIT_DEF), (LASTB_RPZ_H $P1, (INDEX_II_H 0, 1)),
+                sub_32)>;
+  def : Pat<(i64(find_last_active nxv4i1:$P1)),
+            (INSERT_SUBREG(IMPLICIT_DEF), (LASTB_RPZ_S $P1, (INDEX_II_S 0, 1)),
+                sub_32)>;
+  def : Pat<(i64(find_last_active nxv2i1:$P1)), (LASTB_RPZ_D $P1, (INDEX_II_D 0,
+                                                                      1))>;
 
   // Move element from the bottom 128-bits of a scalable vector to a single-element vector.
   // Alternative case where insertelement is just scalar_to_vector rather than vector_insert.