@@ -71,9 +71,8 @@ bool divisible(APInt lhs, APInt rhs) { return !lhs.urem(rhs); }
7171// / -> !xegpu.tensor_desc<4x1xf32>
7272// /
7373// / ```
74- struct WarpOpTensorDescOp final
75- : public OpRewritePattern<gpu::WarpExecuteOnLane0Op> {
76- using OpRewritePattern<gpu::WarpExecuteOnLane0Op>::OpRewritePattern;
74+ struct WarpOpTensorDescOp final : public gpu::WarpDistributionPattern {
75+ using gpu::WarpDistributionPattern::WarpDistributionPattern;
7776 LogicalResult matchAndRewrite (gpu::WarpExecuteOnLane0Op warpOp,
7877 PatternRewriter &rewriter) const override ;
7978};
@@ -107,9 +106,8 @@ struct WarpOpTensorDescOp final
107106// / !xegpu.tensor_desc<4x1xf32>
108107// /
109108// / ```
110- struct WarpOpStoreNd final
111- : public OpRewritePattern<gpu::WarpExecuteOnLane0Op> {
112- using OpRewritePattern<gpu::WarpExecuteOnLane0Op>::OpRewritePattern;
109+ struct WarpOpStoreNd final : public gpu::WarpDistributionPattern {
110+ using gpu::WarpDistributionPattern::WarpDistributionPattern;
113111 LogicalResult matchAndRewrite (gpu::WarpExecuteOnLane0Op warpOp,
114112 PatternRewriter &rewriter) const override ;
115113};
@@ -144,8 +142,8 @@ struct WarpOpStoreNd final
144142// / !xegpu.tensor_desc<4x1xf32>
145143// /
146144// / ```
147- struct WarpOpLoadNd final : public OpRewritePattern< gpu::WarpExecuteOnLane0Op> {
148- using OpRewritePattern< gpu::WarpExecuteOnLane0Op>::OpRewritePattern ;
145+ struct WarpOpLoadNd final : public gpu::WarpDistributionPattern {
146+ using gpu::WarpDistributionPattern::WarpDistributionPattern ;
149147 LogicalResult matchAndRewrite (gpu::WarpExecuteOnLane0Op warpOp,
150148 PatternRewriter &rewriter) const override ;
151149};
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