Skip to content

Commit e7eeecb

Browse files
time out when running test
1 parent 39c2d0c commit e7eeecb

File tree

2 files changed

+14
-3
lines changed

2 files changed

+14
-3
lines changed

llvm/lib/CodeGen/LowLevelTypeUtils.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,9 @@ LLT llvm::getLLTForType(Type &Ty, const DataLayout &DL) {
3636
// concerned.
3737
auto SizeInBits = DL.getTypeSizeInBits(&Ty);
3838
assert(SizeInBits != 0 && "invalid zero-sized type");
39+
if (Ty.isBFloatTy()) {
40+
return LLT::scalar_bfloat(SizeInBits);
41+
}
3942
return LLT::scalar(SizeInBits);
4043
}
4144

@@ -73,9 +76,6 @@ LLT llvm::getLLTForMVT(MVT Ty) {
7376

7477
const llvm::fltSemantics &llvm::getFltSemanticForLLT(LLT Ty) {
7578
assert(Ty.isScalar() && "Expected a scalar type.");
76-
if(Ty.isBfloat()) {
77-
return APFloat::BFloat();
78-
}
7979
switch (Ty.getSizeInBits()) {
8080
case 16:
8181
return APFloat::IEEEhalf();

llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1262,6 +1262,17 @@ void addInstrRequirements(const MachineInstr &MI,
12621262
break;
12631263
}
12641264
case SPIRV::OpTypeFloat: {
1265+
// const MachineBasicBlock *MBB = MI.getParent();
1266+
// const MachineFunction *MF = MBB->getParent();
1267+
// const MachineRegisterInfo &MRI = MF->getRegInfo();
1268+
// const MachineOperand &MO = MI.getOperand(1);
1269+
// if (MO.isReg()) {
1270+
// LLT Ty = MRI.getType(MO.getReg());
1271+
// if(!Ty.isScalar()) {
1272+
// assert(1 && "hola, ur wrong");
1273+
// }
1274+
// }
1275+
12651276
unsigned BitWidth = MI.getOperand(1).getImm();
12661277
if (BitWidth == 64)
12671278
Reqs.addCapability(SPIRV::Capability::Float64);

0 commit comments

Comments
 (0)