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assert
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‎llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4174,6 +4174,14 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
41744174
// Instrument AVX permutation intrinsic.
41754175
// We apply the same permutation (argument index 1) to the shadow.
41764176
void handleAVXPermutation(IntrinsicInst &I) {
4177+
assert(I.arg_size() == 2);
4178+
assert(isa<FixedVectorType>(I.getArgOperand(0)->getType()));
4179+
assert(isa<FixedVectorType>(I.getArgOperand(1)->getType()));
4180+
[[maybe_unused]] auto ArgVectorSize =
4181+
cast<FixedVectorType>(I.getArgOperand(0)->getType())->getNumElements();
4182+
assert(cast<FixedVectorType>(I.getArgOperand(1)->getType())
4183+
->getNumElements() == ArgVectorSize);
4184+
assert(I.getType() == I.getArgOperand(0)->getType());
41774185
IRBuilder<> IRB(&I);
41784186
Value *Shadow = getShadow(&I, 0);
41794187
insertShadowCheck(I.getArgOperand(1), &I);

‎llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl-intrinsics.ll‎

Lines changed: 47 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -8633,18 +8633,18 @@ define <4 x double>@test_int_x86_avx512_permvar_df_256(<4 x double> %x0, <4 x i6
86338633
; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
86348634
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
86358635
; CHECK-NEXT: call void @llvm.donothing()
8636-
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP5]] to i256
8637-
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 0
8636+
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP5]] to <4 x double>
8637+
; CHECK-NEXT: [[TMP6:%.*]] = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> [[TMP3]], <4 x i64> [[X1]])
8638+
; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x double> [[TMP6]] to <4 x i64>
86388639
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i256
86398640
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 0
8640-
; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
8641-
; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]
8642-
; CHECK: [[BB5]]:
8641+
; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]
8642+
; CHECK: [[BB7]]:
86438643
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]
86448644
; CHECK-NEXT: unreachable
8645-
; CHECK: [[BB6]]:
8645+
; CHECK: [[BB8]]:
86468646
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> [[X0]], <4 x i64> [[X1]])
8647-
; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8
8647+
; CHECK-NEXT: store <4 x i64> [[TMP7]], ptr @__msan_retval_tls, align 8
86488648
; CHECK-NEXT: ret <4 x double> [[TMP1]]
86498649
;
86508650
%1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %x0, <4 x i64> %x1)
@@ -8660,26 +8660,26 @@ define <4 x double>@test_int_x86_avx512_mask_permvar_df_256(<4 x double> %x0, <4
86608660
; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 96) to ptr), align 8
86618661
; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
86628662
; CHECK-NEXT: call void @llvm.donothing()
8663-
; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i64> [[TMP8]] to i256
8664-
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP14]], 0
8663+
; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i64> [[TMP8]] to <4 x double>
8664+
; CHECK-NEXT: [[TMP16:%.*]] = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> [[TMP14]], <4 x i64> [[X1]])
8665+
; CHECK-NEXT: [[TMP18:%.*]] = bitcast <4 x double> [[TMP16]] to <4 x i64>
86658666
; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i64> [[TMP11]] to i256
86668667
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP15]], 0
8667-
; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
8668-
; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]
8669-
; CHECK: [[BB7]]:
8668+
; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]
8669+
; CHECK: [[BB9]]:
86708670
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]
86718671
; CHECK-NEXT: unreachable
8672-
; CHECK: [[BB8]]:
8672+
; CHECK: [[BB10]]:
86738673
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> [[X0]], <4 x i64> [[X1]])
86748674
; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>
86758675
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>
86768676
; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP10]], <8 x i1> [[TMP10]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
86778677
; CHECK-NEXT: [[EXTRACT1:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
8678-
; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[EXTRACT1]], <4 x i64> zeroinitializer, <4 x i64> [[TMP13]]
8678+
; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[EXTRACT1]], <4 x i64> [[TMP18]], <4 x i64> [[TMP13]]
86798679
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x double> [[TMP1]] to <4 x i64>
86808680
; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x double> [[X2]] to <4 x i64>
86818681
; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i64> [[TMP4]], [[TMP5]]
8682-
; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i64> [[TMP6]], zeroinitializer
8682+
; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i64> [[TMP6]], [[TMP18]]
86838683
; CHECK-NEXT: [[TMP17:%.*]] = or <4 x i64> [[TMP7]], [[TMP13]]
86848684
; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i64> [[TMP17]], <4 x i64> [[TMP12]]
86858685
; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[EXTRACT1]], <4 x double> [[TMP1]], <4 x double> [[X2]]
@@ -8701,25 +8701,25 @@ define <4 x double>@test_int_x86_avx512_maskz_permvar_df_256(<4 x double> %x0, <
87018701
; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
87028702
; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
87038703
; CHECK-NEXT: call void @llvm.donothing()
8704-
; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i64> [[TMP10]] to i256
8705-
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP13]], 0
8704+
; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i64> [[TMP10]] to <4 x double>
8705+
; CHECK-NEXT: [[TMP15:%.*]] = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> [[TMP13]], <4 x i64> [[X1]])
8706+
; CHECK-NEXT: [[TMP16:%.*]] = bitcast <4 x double> [[TMP15]] to <4 x i64>
87068707
; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i64> [[TMP11]] to i256
87078708
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP14]], 0
8708-
; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
8709-
; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
8710-
; CHECK: [[BB6]]:
8709+
; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]
8710+
; CHECK: [[BB8]]:
87118711
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]
87128712
; CHECK-NEXT: unreachable
8713-
; CHECK: [[BB7]]:
8713+
; CHECK: [[BB9]]:
87148714
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> [[X0]], <4 x i64> [[X1]])
87158715
; CHECK-NEXT: [[TMP9:%.*]] = bitcast i8 [[TMP12]] to <8 x i1>
87168716
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>
87178717
; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i1> [[TMP9]], <8 x i1> [[TMP9]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
87188718
; CHECK-NEXT: [[EXTRACT1:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
8719-
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT1]], <4 x i64> zeroinitializer, <4 x i64> zeroinitializer
8719+
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[EXTRACT1]], <4 x i64> [[TMP16]], <4 x i64> zeroinitializer
87208720
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x double> [[TMP1]] to <4 x i64>
87218721
; CHECK-NEXT: [[TMP5:%.*]] = xor <4 x i64> [[TMP4]], zeroinitializer
8722-
; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i64> [[TMP5]], zeroinitializer
8722+
; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i64> [[TMP5]], [[TMP16]]
87238723
; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i64> [[TMP6]], zeroinitializer
87248724
; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[_MSPROP]], <4 x i64> [[TMP7]], <4 x i64> [[TMP3]]
87258725
; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[EXTRACT1]], <4 x double> [[TMP1]], <4 x double> zeroinitializer
@@ -8741,7 +8741,14 @@ define <4 x i64>@test_int_x86_avx512_permvar_di_256(<4 x i64> %x0, <4 x i64> %x1
87418741
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
87428742
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
87438743
; CHECK-NEXT: call void @llvm.donothing()
8744-
; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP3]], [[TMP2]]
8744+
; CHECK-NEXT: [[_MSPROP:%.*]] = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> [[TMP3]], <4 x i64> [[X1]])
8745+
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i256
8746+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 0
8747+
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]
8748+
; CHECK: [[BB5]]:
8749+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]
8750+
; CHECK-NEXT: unreachable
8751+
; CHECK: [[BB6]]:
87458752
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> [[X0]], <4 x i64> [[X1]])
87468753
; CHECK-NEXT: store <4 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8
87478754
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
@@ -8759,7 +8766,14 @@ define <4 x i64>@test_int_x86_avx512_mask_permvar_di_256(<4 x i64> %x0, <4 x i64
87598766
; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 96) to ptr), align 8
87608767
; CHECK-NEXT: [[TMP12:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
87618768
; CHECK-NEXT: call void @llvm.donothing()
8762-
; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP5]], [[TMP9]]
8769+
; CHECK-NEXT: [[_MSPROP:%.*]] = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> [[TMP5]], <4 x i64> [[X1]])
8770+
; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i64> [[TMP9]] to i256
8771+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP13]], 0
8772+
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]
8773+
; CHECK: [[BB7]]:
8774+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]
8775+
; CHECK-NEXT: unreachable
8776+
; CHECK: [[BB8]]:
87638777
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> [[X0]], <4 x i64> [[X1]])
87648778
; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>
87658779
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>
@@ -8789,7 +8803,14 @@ define <4 x i64>@test_int_x86_avx512_maskz_permvar_di_256(<4 x i64> %x0, <4 x i6
87898803
; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
87908804
; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
87918805
; CHECK-NEXT: call void @llvm.donothing()
8792-
; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP8]], [[TMP9]]
8806+
; CHECK-NEXT: [[_MSPROP:%.*]] = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> [[TMP8]], <4 x i64> [[X1]])
8807+
; CHECK-NEXT: [[TMP12:%.*]] = bitcast <4 x i64> [[TMP9]] to i256
8808+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP12]], 0
8809+
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
8810+
; CHECK: [[BB6]]:
8811+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]
8812+
; CHECK-NEXT: unreachable
8813+
; CHECK: [[BB7]]:
87938814
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> [[X0]], <4 x i64> [[X1]])
87948815
; CHECK-NEXT: [[TMP10:%.*]] = bitcast i8 [[TMP3]] to <8 x i1>
87958816
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8 [[X3]] to <8 x i1>

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