Address review comments

Author: spavloff

llvm/lib/Target/ARM/ARMInstructionSelector.cpp

@@ -14,6 +14,7 @@
 #include "ARMSubtarget.h"
 #include "ARMTargetMachine.h"
 #include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
+#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -1088,7 +1089,7 @@ bool ARMInstructionSelector::select(MachineInstr &I) {
     return selectGlobal(MIB, MRI);
   case G_STORE:
   case G_LOAD: {
-    const auto &MemOp = **I.memoperands_begin();
+    auto &MemOp = **I.memoperands_begin();
     if (MemOp.isAtomic()) {
       LLVM_DEBUG(dbgs() << "Atomic load/store not supported yet\n");
       return false;
@@ -1103,24 +1104,28 @@ bool ARMInstructionSelector::select(MachineInstr &I) {
     assert((ValSize != 64 || STI.hasVFP2Base()) &&
            "Don't know how to load/store 64-bit value without VFP");
 
-    MachineInstr *Ptr = MRI.getVRegDef(I.getOperand(1).getReg());
-    if (Ptr->getOpcode() == TargetOpcode::G_CONSTANT_POOL) {
-      unsigned Opcode;
-      if (Subtarget->isThumb())
-        Opcode = ARM::tLDRpci;
-      else
-        Opcode = ARM::LDRcp;
-
-      auto Instr = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
-                       .addDef(Reg)
-                       .add(Ptr->getOperand(1))
-                       .addImm(0)
-                       .add(predOps(ARMCC::AL))
-                       .addMemOperand(I.memoperands().front());
-      if (!constrainSelectedInstRegOperands(*Instr, TII, TRI, RBI))
-        return false;
-      I.eraseFromParent();
-      return true;
+    if (auto *LoadMI = dyn_cast<GLoad>(&I)) {
+      Register PtrReg = LoadMI->getPointerReg();
+      MachineInstr *Ptr = MRI.getVRegDef(PtrReg);
+      if (Ptr->getOpcode() == TargetOpcode::G_CONSTANT_POOL) {
+        const MachineOperand &Index = Ptr->getOperand(1);
+        unsigned Opcode;
+        if (Subtarget->isThumb())
+          Opcode = ARM::tLDRpci;
+        else
+          Opcode = ARM::LDRcp;
+
+        auto Instr = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
+                         .addDef(Reg)
+                         .add(Index)
+                         .addImm(0)
+                         .add(predOps(ARMCC::AL))
+                         .addMemOperand(&MemOp);
+        if (!constrainSelectedInstRegOperands(*Instr, TII, TRI, RBI))
+          return false;
+        I.eraseFromParent();
+        return true;
+      }
     }
 
     const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize);

llvm/lib/Target/ARM/ARMLegalizerInfo.cpp

@@ -29,7 +29,7 @@ static bool AEABI(const ARMSubtarget &ST) {
   return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
 }
 
-ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) : ST(&ST) {
+ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) : ST(ST) {
   using namespace TargetOpcode;
 
   const LLT p0 = LLT::pointer(0, 32);
@@ -440,8 +440,7 @@ bool ARMLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
   case G_CONSTANT: {
     const ConstantInt *ConstVal = MI.getOperand(1).getCImm();
     uint64_t ImmVal = ConstVal->getZExtValue();
-    if (ConstantMaterializationCost(ImmVal, ST) > 2 &&
-        !ST->genExecuteOnly())
+    if (ConstantMaterializationCost(ImmVal, &ST) > 2 && !ST.genExecuteOnly())
       return Helper.lowerConstant(MI) == LegalizerHelper::Legalized;
     return true;
   }

llvm/lib/Target/ARM/ARMLegalizerInfo.h

@@ -60,7 +60,7 @@ class ARMLegalizerInfo : public LegalizerInfo {
   // bits.
   FCmpLibcallsList getFCmpLibcalls(CmpInst::Predicate, unsigned Size) const;
 
-  const ARMSubtarget *ST;
+  const ARMSubtarget &ST;
 };
 } // End llvm namespace.
 #endif

llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-const.mir

@@ -1,12 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
 # RUN: llc -mtriple arm-- -run-pass=legalizer %s -o - | FileCheck %s
 
---- |
-  define i32 @get_const() {
-  entry:
-    ret i32 287454020
-  }
-...
 ---
 name:            get_const
 legalized:       false

llvm/test/CodeGen/ARM/GlobalISel/select-constpool.mir

@@ -1,12 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
 # RUN: llc -mtriple arm-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 
---- |
-  define i32 @get_const() {
-  entry:
-    ret i32 287454020
-  }
-...
 ---
 name:            get_const
 legalized:       true