Updated the comments and testcase updated.

Author: ukalappa-mips

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

@@ -573,7 +573,6 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
     int64_t Val = Offset.getFixed();
     int64_t Lo12 = SignExtend64<12>(Val);
     unsigned Opc = MI.getOpcode();
-    int64_t Imm9Val = SignExtend64<9>(Val);
     auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
 
     if (Opc == RISCV::ADDI && !isInt<12>(Val)) {
@@ -588,9 +587,8 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
                (Lo12 & 0b11111) != 0) {
       // Prefetch instructions require the offset to be 32 byte aligned.
       MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
-    } else if ((Opc == RISCV::PREFETCH_I || Opc == RISCV::PREFETCH_R ||
-                Opc == RISCV::PREFETCH_W) &&
-               Subtarget.hasVendorXMIPSCBOP() && !isUInt<9>(Imm9Val)) {
+    } else if (Opc == RISCV::MIPS_PREFETCH && Subtarget.hasVendorXMIPSCBOP() &&
+               !isUInt<9>(Val)) {
       // MIPS Prefetch instructions require the offset to be 9 bits encoded.
       MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
     } else if ((Opc == RISCV::PseudoRV32ZdinxLD ||

llvm/test/CodeGen/RISCV/xmips-cbop.ll

@@ -53,22 +53,30 @@ define void @prefetch_inst_read(ptr noundef %ptr) nounwind  {
 define void @prefetch_frameindex_test_neg() nounwind {
 ; RV32XMIPSPREFETCH-LABEL: prefetch_frameindex_test_neg:
 ; RV32XMIPSPREFETCH:       # %bb.0:
-; RV32XMIPSPREFETCH-NEXT:    addi sp, sp, -512
-; RV32XMIPSPREFETCH-NEXT:    addi a0, sp, -32
+; RV32XMIPSPREFETCH-NEXT:    lui a0, 1
+; RV32XMIPSPREFETCH-NEXT:    addi a0, a0, 16
+; RV32XMIPSPREFETCH-NEXT:    sub sp, sp, a0
+; RV32XMIPSPREFETCH-NEXT:    addi a0, sp, 524
 ; RV32XMIPSPREFETCH-NEXT:    mips.pref 8, 0(a0)
-; RV32XMIPSPREFETCH-NEXT:    addi sp, sp, 512
+; RV32XMIPSPREFETCH-NEXT:    lui a0, 1
+; RV32XMIPSPREFETCH-NEXT:    addi a0, a0, 16
+; RV32XMIPSPREFETCH-NEXT:    add sp, sp, a0
 ; RV32XMIPSPREFETCH-NEXT:    ret
 ;
 ; RV64XMIPSPREFETCH-LABEL: prefetch_frameindex_test_neg:
 ; RV64XMIPSPREFETCH:       # %bb.0:
-; RV64XMIPSPREFETCH-NEXT:    addi sp, sp, -512
-; RV64XMIPSPREFETCH-NEXT:    addi a0, sp, -32
+; RV64XMIPSPREFETCH-NEXT:    lui a0, 1
+; RV64XMIPSPREFETCH-NEXT:    addi a0, a0, 16
+; RV64XMIPSPREFETCH-NEXT:    sub sp, sp, a0
+; RV64XMIPSPREFETCH-NEXT:    addi a0, sp, 524
 ; RV64XMIPSPREFETCH-NEXT:    mips.pref 8, 0(a0)
-; RV64XMIPSPREFETCH-NEXT:    addi sp, sp, 512
+; RV64XMIPSPREFETCH-NEXT:    lui a0, 1
+; RV64XMIPSPREFETCH-NEXT:    addi a0, a0, 16
+; RV64XMIPSPREFETCH-NEXT:    add sp, sp, a0
 ; RV64XMIPSPREFETCH-NEXT:    ret
- %data = alloca [128 x i32], align 4
+  %data = alloca [1024 x i32], align 4
   %base = bitcast ptr %data to ptr
-  %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 -8
+  %ptr = getelementptr [127 x i32], ptr %base, i32 0, i32 127
   call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
   ret void
 }
@@ -87,7 +95,7 @@ define void @prefetch_frameindex_test() nounwind {
 ; RV64XMIPSPREFETCH-NEXT:    mips.pref 8, 32(sp)
 ; RV64XMIPSPREFETCH-NEXT:    addi sp, sp, 512
 ; RV64XMIPSPREFETCH-NEXT:    ret
- %data = alloca [128 x i32], align 4
+  %data = alloca [128 x i32], align 4
   %base = bitcast ptr %data to ptr
   %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 8
   call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)