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fixup! [RISCV][VLS] Support RISCV VLS calling convention
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3 files changed

+55
-55
lines changed

3 files changed

+55
-55
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‎clang/lib/CodeGen/Targets/RISCV.cpp‎

Lines changed: 40 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -120,42 +120,23 @@ void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const {
120120
default:
121121
ABIVLen = 0;
122122
break;
123-
case CallingConv::CC_RISCVVLSCall_32:
124-
ABIVLen = 32;
125-
break;
126-
case CallingConv::CC_RISCVVLSCall_64:
127-
ABIVLen = 64;
128-
break;
129-
case CallingConv::CC_RISCVVLSCall_128:
130-
ABIVLen = 128;
131-
break;
132-
case CallingConv::CC_RISCVVLSCall_256:
133-
ABIVLen = 256;
134-
break;
135-
case CallingConv::CC_RISCVVLSCall_512:
136-
ABIVLen = 512;
137-
break;
138-
case CallingConv::CC_RISCVVLSCall_1024:
139-
ABIVLen = 1024;
140-
break;
141-
case CallingConv::CC_RISCVVLSCall_2048:
142-
ABIVLen = 2048;
143-
break;
144-
case CallingConv::CC_RISCVVLSCall_4096:
145-
ABIVLen = 4096;
146-
break;
147-
case CallingConv::CC_RISCVVLSCall_8192:
148-
ABIVLen = 8192;
149-
break;
150-
case CallingConv::CC_RISCVVLSCall_16384:
151-
ABIVLen = 16384;
152-
break;
153-
case CallingConv::CC_RISCVVLSCall_32768:
154-
ABIVLen = 32768;
155-
break;
156-
case CallingConv::CC_RISCVVLSCall_65536:
157-
ABIVLen = 65536;
123+
#define CC_VLS_CASE(ABI_VLEN) \
124+
case CallingConv::CC_RISCVVLSCall_##ABI_VLEN: \
125+
ABIVLen = ABI_VLEN; \
158126
break;
127+
CC_VLS_CASE(32)
128+
CC_VLS_CASE(64)
129+
CC_VLS_CASE(128)
130+
CC_VLS_CASE(256)
131+
CC_VLS_CASE(512)
132+
CC_VLS_CASE(1024)
133+
CC_VLS_CASE(2048)
134+
CC_VLS_CASE(4096)
135+
CC_VLS_CASE(8192)
136+
CC_VLS_CASE(16384)
137+
CC_VLS_CASE(32768)
138+
CC_VLS_CASE(65536)
139+
#undef CC_VLS_CASE
159140
}
160141
QualType RetTy = FI.getReturnType();
161142
if (!getCXXABI().classifyReturnType(FI))
@@ -466,7 +447,7 @@ bool RISCVABIInfo::detectVLSCCEligibleStruct(QualType Ty, unsigned ABIVLen,
466447
// Otherwise, pass the struct indirectly.
467448

468449
if (llvm::StructType *STy = dyn_cast<llvm::StructType>(CGT.ConvertType(Ty))) {
469-
int NumElts = STy->getStructNumElements();
450+
unsigned NumElts = STy->getStructNumElements();
470451
if (NumElts > 8)
471452
return false;
472453

@@ -522,7 +503,7 @@ bool RISCVABIInfo::detectVLSCCEligibleStruct(QualType Ty, unsigned ABIVLen,
522503
// Check array of fixed-length vector and turn it into scalable vector type
523504
// if legal.
524505
if (auto *ArrTy = dyn_cast<llvm::ArrayType>(FirstEltTy)) {
525-
int NumArrElt = ArrTy->getNumElements();
506+
unsigned NumArrElt = ArrTy->getNumElements();
526507
if (NumArrElt > 8)
527508
return false;
528509

@@ -595,17 +576,6 @@ ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty, unsigned ABIVLen) const {
595576
// * (RVVBitsPerBlock / EltSize)
596577
ResType = llvm::ScalableVectorType::get(EltType, NumElts / VScale->first);
597578
} else {
598-
// If the corresponding extension is not supported, just make it an i32
599-
// vector.
600-
const TargetInfo &TI = getContext().getTargetInfo();
601-
if ((EltType->isHalfTy() && !TI.hasFeature("zvfhmin")) ||
602-
(EltType->isBFloatTy() && !TI.hasFeature("zvfbfmin")) ||
603-
(EltType->isFloatTy() && !TI.hasFeature("zve32f")) ||
604-
(EltType->isDoubleTy() && !TI.hasFeature("zve64d")) ||
605-
EltType->isIntegerTy(128))
606-
EltType =
607-
llvm::Type::getIntNTy(getVMContext(), EltType->getScalarSizeInBits());
608-
609579
// Check registers needed <= 8.
610580
if ((EltType->getScalarSizeInBits() * NumElts / ABIVLen) > 8)
611581
return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
@@ -615,6 +585,23 @@ ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty, unsigned ABIVLen) const {
615585
ResType = llvm::ScalableVectorType::get(
616586
EltType,
617587
llvm::divideCeil(NumElts * llvm::RISCV::RVVBitsPerBlock, ABIVLen));
588+
589+
// If the corresponding extension is not supported, just make it an i8
590+
// vector with same LMUL.
591+
const TargetInfo &TI = getContext().getTargetInfo();
592+
if ((EltType->isHalfTy() && !TI.hasFeature("zvfhmin")) ||
593+
(EltType->isBFloatTy() && !TI.hasFeature("zvfbfmin")) ||
594+
(EltType->isFloatTy() && !TI.hasFeature("zve32f")) ||
595+
(EltType->isDoubleTy() && !TI.hasFeature("zve64d")) ||
596+
(EltType->isIntegerTy(64) && !TI.hasFeature("zve64x")) ||
597+
EltType->isIntegerTy(128)) {
598+
// The number of elements needs to be at least 1.
599+
ResType = llvm::ScalableVectorType::get(
600+
llvm::Type::getInt8Ty(getVMContext()),
601+
llvm::divideCeil(EltType->getScalarSizeInBits() * NumElts *
602+
llvm::RISCV::RVVBitsPerBlock,
603+
8 * ABIVLen));
604+
}
618605
}
619606

620607
return ABIArgInfo::getDirect(ResType);
@@ -726,7 +713,11 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
726713
return ABIArgInfo::getDirect();
727714
}
728715

729-
if (const VectorType *VT = Ty->getAs<VectorType>()) {
716+
// TODO: _BitInt is not handled yet in VLS calling convention since _BitInt
717+
// ABI is also not merged yet in RISCV:
718+
// https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/419
719+
if (const VectorType *VT = Ty->getAs<VectorType>();
720+
VT && !VT->getElementType()->isBitIntType()) {
730721
if (VT->getVectorKind() == VectorKind::RVVFixedLengthData ||
731722
VT->getVectorKind() == VectorKind::RVVFixedLengthMask ||
732723
VT->getVectorKind() == VectorKind::RVVFixedLengthMask_1 ||

‎clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c‎

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -44,18 +44,24 @@ void __attribute__((riscv_vls_cc)) test_vls_default_abi_vlen(__attribute__((vect
4444
// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_c23(<vscale x 2 x i32> noundef %arg.coerce)
4545
[[riscv::vls_cc]] void test_vls_default_abi_vlen_c23(__attribute__((vector_size(16))) int arg) {}
4646

47-
// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_unsupported_feature(<vscale x 4 x i16> noundef %arg.coerce)
47+
// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_unsupported_feature(<vscale x 8 x i8> noundef %arg.coerce)
4848
void __attribute__((riscv_vls_cc)) test_vls_default_abi_vlen_unsupported_feature(__attribute__((vector_size(16))) _Float16 arg) {}
4949

50-
// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_c23_unsupported_feature(<vscale x 4 x i16> noundef %arg.coerce)
50+
// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_c23_unsupported_feature(<vscale x 8 x i8> noundef %arg.coerce)
5151
[[riscv::vls_cc]] void test_vls_default_abi_vlen_c23_unsupported_feature(__attribute__((vector_size(16))) _Float16 arg) {}
5252

53-
// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_unsupported_feature_zve32x(<vscale x 2 x i32> noundef %arg.coerce)
53+
// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_unsupported_feature_zve32x(<vscale x 8 x i8> noundef %arg.coerce)
5454
void __attribute__((riscv_vls_cc)) test_vls_default_abi_vlen_unsupported_feature_zve32x(__attribute__((vector_size(16))) float arg) {}
5555

56-
// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_c23_unsupported_feature_zve32x(<vscale x 2 x i32> noundef %arg.coerce)
56+
// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_c23_unsupported_feature_zve32x(<vscale x 8 x i8> noundef %arg.coerce)
5757
[[riscv::vls_cc]] void test_vls_default_abi_vlen_c23_unsupported_feature_zve32x(__attribute__((vector_size(16))) float arg) {}
5858

59+
// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_unsupported_feature_no_zve64x(<vscale x 8 x i8> noundef %arg.coerce)
60+
void __attribute__((riscv_vls_cc)) test_vls_default_abi_vlen_unsupported_feature_no_zve64x(__attribute__((vector_size(16))) uint64_t arg) {}
61+
62+
// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_c23_unsupported_feature_no_zve64x(<vscale x 8 x i8> noundef %arg.coerce)
63+
[[riscv::vls_cc]] void test_vls_default_abi_vlen_c23_unsupported_feature_no_zve64x(__attribute__((vector_size(16))) uint64_t arg) {}
64+
5965
// CHECK-LLVM: define dso_local riscv_vls_cc(256) void @test_vls_256_abi_vlen(<vscale x 1 x i32> noundef %arg.coerce)
6066
void __attribute__((riscv_vls_cc(256))) test_vls_256_abi_vlen(__attribute__((vector_size(16))) int arg) {}
6167

‎clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -39,12 +39,15 @@ void test_vls_no_cc(__attribute__((vector_size(16))) int arg) {}
3939
// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z25test_vls_default_abi_vlenDv4_i(<vscale x 2 x i32> noundef %arg.coerce)
4040
[[riscv::vls_cc]] void test_vls_default_abi_vlen(__attribute__((vector_size(16))) int arg) {}
4141

42-
// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z45test_vls_default_abi_vlen_unsupported_featureDv8_DF16_(<vscale x 4 x i16> noundef %arg.coerce)
42+
// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z45test_vls_default_abi_vlen_unsupported_featureDv8_DF16_(<vscale x 8 x i8> noundef %arg.coerce)
4343
[[riscv::vls_cc]] void test_vls_default_abi_vlen_unsupported_feature(__attribute__((vector_size(16))) _Float16 arg) {}
4444

45-
// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @_Z52test_vls_default_abi_vlen_unsupported_feature_zve32xDv4_f(<vscale x 2 x i32> noundef %arg.coerce)
45+
// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @_Z52test_vls_default_abi_vlen_unsupported_feature_zve32xDv4_f(<vscale x 8 x i8> noundef %arg.coerce)
4646
[[riscv::vls_cc]] void test_vls_default_abi_vlen_unsupported_feature_zve32x(__attribute__((vector_size(16))) float arg) {}
4747

48+
// CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @_Z55test_vls_default_abi_vlen_unsupported_feature_no_zve64xDv2_m(<vscale x 8 x i8> noundef %arg.coerce)
49+
[[riscv::vls_cc]] void test_vls_default_abi_vlen_unsupported_feature_no_zve64x(__attribute__((vector_size(16))) uint64_t arg) {}
50+
4851
// CHECK-LLVM: define dso_local riscv_vls_cc(256) void @_Z21test_vls_256_abi_vlenDv4_i(<vscale x 1 x i32> noundef %arg.coerce)
4952
[[riscv::vls_cc(256)]] void test_vls_256_abi_vlen(__attribute__((vector_size(16))) int arg) {}
5053

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