AMDGPU: Set RegTupleAlignUnits on _Lo256_Align2 class (#159383)

arsenm · web-flow · commit e86a8e33f917 · 2025-09-18T07:27:47.000+09:00
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -1025,7 +1025,9 @@ multiclass VRegClass<int numRegs, list<ValueType> regTypes, dag regList> {
 
     // Aligned register tuples starting with low 256 vgprs
     def _Lo256_Align2 : VRegClassBase<numRegs, regTypes,
-        (trunc (decimate regList, 2), !div(!sub(258, numRegs), 2))>;
+        (trunc (decimate regList, 2), !div(!sub(258, numRegs), 2))> {
+      let RegTupleAlignUnits = 2;
+     }
   }
 }
 

Original file line number	Diff line number	Diff line change
`@@ -1025,7 +1025,9 @@ multiclass VRegClass<int numRegs, list<ValueType> regTypes, dag regList> {`
`1025`	`1025`
`1026`	`1026`	`// Aligned register tuples starting with low 256 vgprs`
`1027`	`1027`	`def _Lo256_Align2 : VRegClassBase<numRegs, regTypes,`
`1028`		`- (trunc (decimate regList, 2), !div(!sub(258, numRegs), 2))>;`
	`1028`	`+ (trunc (decimate regList, 2), !div(!sub(258, numRegs), 2))> {`
	`1029`	`+ let RegTupleAlignUnits = 2;`
	`1030`	`+ }`
`1029`	`1031`	`}`
`1030`	`1032`	`}`
`1031`	`1033`