@@ -3629,7 +3629,7 @@ class ARMOperand : public MCParsedAsmOperand {
36293629 Inst.addOperand (MCOperand::createImm (Imm == 48 ? 1 : 0 ));
36303630 }
36313631
3632- void print (raw_ostream &OS) const override ;
3632+ void print (raw_ostream &OS, const MCAsmInfo &MAI ) const override ;
36333633
36343634 static std::unique_ptr<ARMOperand> CreateITMask (unsigned Mask, SMLoc S,
36353635 ARMAsmParser &Parser) {
@@ -3979,7 +3979,7 @@ class ARMOperand : public MCParsedAsmOperand {
39793979
39803980} // end anonymous namespace.
39813981
3982- void ARMOperand::print (raw_ostream &OS) const {
3982+ void ARMOperand::print (raw_ostream &OS, const MCAsmInfo &MAI ) const {
39833983 auto RegName = [](MCRegister Reg) {
39843984 if (Reg)
39853985 return ARMInstPrinter::getRegisterName (Reg);
@@ -4024,7 +4024,7 @@ void ARMOperand::print(raw_ostream &OS) const {
40244024 OS << " <banked reg: " << getBankedReg () << " >" ;
40254025 break ;
40264026 case k_Immediate:
4027- MCAsmInfo () .printExpr (OS, *getImm ());
4027+ MAI .printExpr (OS, *getImm ());
40284028 break ;
40294029 case k_MemBarrierOpt:
40304030 OS << " <ARM_MB::" << MemBOptToString (getMemBarrierOpt (), false ) << " >" ;
@@ -4041,7 +4041,7 @@ void ARMOperand::print(raw_ostream &OS) const {
40414041 OS << " base:" << RegName (Memory.BaseRegNum );
40424042 if (Memory.OffsetImm ) {
40434043 OS << " offset-imm:" ;
4044- MCAsmInfo () .printExpr (OS, *Memory.OffsetImm );
4044+ MAI .printExpr (OS, *Memory.OffsetImm );
40454045 }
40464046 if (Memory.OffsetRegNum )
40474047 OS << " offset-reg:" << (Memory.isNegative ? " -" : " " )
@@ -4097,7 +4097,7 @@ void ARMOperand::print(raw_ostream &OS) const {
40974097 break ;
40984098 case k_ConstantPoolImmediate:
40994099 OS << " <constant_pool_imm #" ;
4100- MCAsmInfo () .printExpr (OS, *getConstantPoolImm ());
4100+ MAI .printExpr (OS, *getConstantPoolImm ());
41014101 break ;
41024102 case k_BitfieldDescriptor:
41034103 OS << " <bitfield " << " lsb: " << Bitfield.LSB
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