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Update tests after rebase.
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-24
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+24
-24
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‎llvm/test/CodeGen/AArch64/abds-neg.ll‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -77,8 +77,8 @@ define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
7777
; CHECK-LABEL: abd_ext_i16_i32:
7878
; CHECK: // %bb.0:
7979
; CHECK-NEXT: sxth w8, w0
80-
; CHECK-NEXT: subs w8, w1, w8
81-
; CHECK-NEXT: cneg w0, w8, ge
80+
; CHECK-NEXT: subs w8, w8, w1
81+
; CHECK-NEXT: cneg w0, w8, gt
8282
; CHECK-NEXT: ret
8383
%aext = sext i16 %a to i64
8484
%bext = sext i32 %b to i64
@@ -109,8 +109,8 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
109109
define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
110110
; CHECK-LABEL: abd_ext_i32:
111111
; CHECK: // %bb.0:
112-
; CHECK-NEXT: subs w8, w1, w0
113-
; CHECK-NEXT: cneg w0, w8, ge
112+
; CHECK-NEXT: subs w8, w0, w1
113+
; CHECK-NEXT: cneg w0, w8, gt
114114
; CHECK-NEXT: ret
115115
%aext = sext i32 %a to i64
116116
%bext = sext i32 %b to i64
@@ -125,8 +125,8 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
125125
; CHECK-LABEL: abd_ext_i32_i16:
126126
; CHECK: // %bb.0:
127127
; CHECK-NEXT: sxth w8, w1
128-
; CHECK-NEXT: subs w8, w8, w0
129-
; CHECK-NEXT: cneg w0, w8, ge
128+
; CHECK-NEXT: subs w8, w0, w8
129+
; CHECK-NEXT: cneg w0, w8, gt
130130
; CHECK-NEXT: ret
131131
%aext = sext i32 %a to i64
132132
%bext = sext i16 %b to i64
@@ -140,8 +140,8 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
140140
define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
141141
; CHECK-LABEL: abd_ext_i32_undef:
142142
; CHECK: // %bb.0:
143-
; CHECK-NEXT: subs w8, w1, w0
144-
; CHECK-NEXT: cneg w0, w8, ge
143+
; CHECK-NEXT: subs w8, w0, w1
144+
; CHECK-NEXT: cneg w0, w8, gt
145145
; CHECK-NEXT: ret
146146
%aext = sext i32 %a to i64
147147
%bext = sext i32 %b to i64
@@ -155,8 +155,8 @@ define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
155155
define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
156156
; CHECK-LABEL: abd_ext_i64:
157157
; CHECK: // %bb.0:
158-
; CHECK-NEXT: subs x8, x1, x0
159-
; CHECK-NEXT: cneg x0, x8, ge
158+
; CHECK-NEXT: subs x8, x0, x1
159+
; CHECK-NEXT: cneg x0, x8, gt
160160
; CHECK-NEXT: ret
161161
%aext = sext i64 %a to i128
162162
%bext = sext i64 %b to i128
@@ -170,8 +170,8 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
170170
define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
171171
; CHECK-LABEL: abd_ext_i64_undef:
172172
; CHECK: // %bb.0:
173-
; CHECK-NEXT: subs x8, x1, x0
174-
; CHECK-NEXT: cneg x0, x8, ge
173+
; CHECK-NEXT: subs x8, x0, x1
174+
; CHECK-NEXT: cneg x0, x8, gt
175175
; CHECK-NEXT: ret
176176
%aext = sext i64 %a to i128
177177
%bext = sext i64 %b to i128

‎llvm/test/CodeGen/AArch64/abdu-neg.ll‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -77,8 +77,8 @@ define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
7777
; CHECK-LABEL: abd_ext_i16_i32:
7878
; CHECK: // %bb.0:
7979
; CHECK-NEXT: and w8, w0, #0xffff
80-
; CHECK-NEXT: subs w8, w1, w8
81-
; CHECK-NEXT: cneg w0, w8, hs
80+
; CHECK-NEXT: subs w8, w8, w1
81+
; CHECK-NEXT: cneg w0, w8, hi
8282
; CHECK-NEXT: ret
8383
%aext = zext i16 %a to i64
8484
%bext = zext i32 %b to i64
@@ -109,8 +109,8 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
109109
define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
110110
; CHECK-LABEL: abd_ext_i32:
111111
; CHECK: // %bb.0:
112-
; CHECK-NEXT: subs w8, w1, w0
113-
; CHECK-NEXT: cneg w0, w8, hs
112+
; CHECK-NEXT: subs w8, w0, w1
113+
; CHECK-NEXT: cneg w0, w8, hi
114114
; CHECK-NEXT: ret
115115
%aext = zext i32 %a to i64
116116
%bext = zext i32 %b to i64
@@ -125,8 +125,8 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
125125
; CHECK-LABEL: abd_ext_i32_i16:
126126
; CHECK: // %bb.0:
127127
; CHECK-NEXT: and w8, w1, #0xffff
128-
; CHECK-NEXT: subs w8, w8, w0
129-
; CHECK-NEXT: cneg w0, w8, hs
128+
; CHECK-NEXT: subs w8, w0, w8
129+
; CHECK-NEXT: cneg w0, w8, hi
130130
; CHECK-NEXT: ret
131131
%aext = zext i32 %a to i64
132132
%bext = zext i16 %b to i64
@@ -140,8 +140,8 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
140140
define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
141141
; CHECK-LABEL: abd_ext_i32_undef:
142142
; CHECK: // %bb.0:
143-
; CHECK-NEXT: subs w8, w1, w0
144-
; CHECK-NEXT: cneg w0, w8, hs
143+
; CHECK-NEXT: subs w8, w0, w1
144+
; CHECK-NEXT: cneg w0, w8, hi
145145
; CHECK-NEXT: ret
146146
%aext = zext i32 %a to i64
147147
%bext = zext i32 %b to i64
@@ -155,8 +155,8 @@ define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
155155
define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
156156
; CHECK-LABEL: abd_ext_i64:
157157
; CHECK: // %bb.0:
158-
; CHECK-NEXT: subs x8, x1, x0
159-
; CHECK-NEXT: cneg x0, x8, hs
158+
; CHECK-NEXT: subs x8, x0, x1
159+
; CHECK-NEXT: cneg x0, x8, hi
160160
; CHECK-NEXT: ret
161161
%aext = zext i64 %a to i128
162162
%bext = zext i64 %b to i128
@@ -170,8 +170,8 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
170170
define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
171171
; CHECK-LABEL: abd_ext_i64_undef:
172172
; CHECK: // %bb.0:
173-
; CHECK-NEXT: subs x8, x1, x0
174-
; CHECK-NEXT: cneg x0, x8, hs
173+
; CHECK-NEXT: subs x8, x0, x1
174+
; CHECK-NEXT: cneg x0, x8, hi
175175
; CHECK-NEXT: ret
176176
%aext = zext i64 %a to i128
177177
%bext = zext i64 %b to i128

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