Test commit: add a parameter to keep reserved

Author: wangpc-pp

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

@@ -914,8 +914,10 @@ class TargetRegisterInfo : public MCRegisterInfo {
 
   /// Get the register unit pressure limit for this dimension.
   /// This limit must be adjusted dynamically for reserved registers.
+  /// If RemoveReserved is true, the target should remove reserved registers.
   virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
-                                          unsigned Idx) const = 0;
+                                          unsigned Idx,
+                                          bool RemoveReserved = true) const = 0;
 
   /// Get the dimensions of register pressure impacted by this register class.
   /// Returns a -1 terminated array of pressure set IDs.

llvm/lib/CodeGen/RegisterClassInfo.cpp

@@ -222,7 +222,8 @@ unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
   assert(RC && "Failed to find register class");
   compute(RC);
   unsigned NAllocatableRegs = getNumAllocatableRegs(RC);
-  unsigned RegPressureSetLimit = TRI->getRegPressureSetLimit(*MF, Idx);
+  unsigned RegPressureSetLimit =
+      TRI->getRegPressureSetLimit(*MF, Idx, /*RemoveReserved=*/false);
   // If all the regs are reserved, return raw RegPressureSetLimit.
   // One example is VRSAVERC in PowerPC.
   // Avoid returning zero, getRegPressureSetLimit(Idx) assumes computePSetLimit

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

@@ -3640,7 +3640,8 @@ unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
 }
 
 unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
-                                                unsigned Idx) const {
+                                                unsigned Idx,
+                                                bool RemoveReserved) const {
   if (Idx == AMDGPU::RegisterPressureSets::VGPR_32 ||
       Idx == AMDGPU::RegisterPressureSets::AGPR_32)
     return getRegPressureLimit(&AMDGPU::VGPR_32RegClass,

llvm/lib/Target/AMDGPU/SIRegisterInfo.h

@@ -331,8 +331,8 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
                                MachineFunction &MF) const override;
 
-  unsigned getRegPressureSetLimit(const MachineFunction &MF,
-                                  unsigned Idx) const override;
+  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx,
+                                  bool RemoveReserved = true) const override;
 
   const int *getRegUnitPressureSets(unsigned RegUnit) const override;
 

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

@@ -936,8 +936,12 @@ bool RISCVRegisterInfo::getRegAllocationHints(
 }
 
 unsigned RISCVRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
-                                                   unsigned Idx) const {
+                                                   unsigned Idx,
+                                                   bool RemoveReserved) const {
   if (Idx == RISCV::RegisterPressureSets::GPRAll) {
+    if (!RemoveReserved)
+      return 32;
+
     unsigned Reserved = 0;
     BitVector ReservedRegs = getReservedRegs(MF);
     for (MCPhysReg Reg = RISCV::X0_H; Reg <= RISCV::X31_H; Reg++)
@@ -946,5 +950,5 @@ unsigned RISCVRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
 
     return 32 - Reserved;
   }
-  return RISCVGenRegisterInfo::getRegPressureSetLimit(MF, Idx);
+  return RISCVGenRegisterInfo::getRegPressureSetLimit(MF, Idx, RemoveReserved);
 }

llvm/lib/Target/RISCV/RISCVRegisterInfo.h

@@ -144,8 +144,8 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
   static bool isRVVRegClass(const TargetRegisterClass *RC) {
     return RISCVRI::isVRegClass(RC->TSFlags);
   }
-  unsigned getRegPressureSetLimit(const MachineFunction &MF,
-                                  unsigned Idx) const override;
+  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx,
+                                  bool RemoveReserved = true) const override;
 };
 } // namespace llvm