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[AArch64] Add assembly/disassembly for SVE COMPACT (b/h) and EXPAND
- Add assembler support for the following SVE2p2 instructions - COMPACT (byte, halfword) - EXPAND - Rename predicates guarding instructions that are illegal in streaming SVE mode without FEAT_SME2p2 Co-authored-by: Marian Lukac [email protected]
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10 files changed

+320
-15
lines changed

10 files changed

+320
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lines changed

‎llvm/lib/Target/AArch64/AArch64.td‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,8 @@ def SVEUnsupported : AArch64Unsupported {
7373
SVE2Unsupported.F);
7474
}
7575

76-
let F = [HasSME2p2, HasSVE2p2orSME2p2] in
76+
let F = [HasSME2p2, HasSVE2p2orSME2p2, HasNonStreamingSVEorSME2p2,
77+
HasNonStreamingSVE2p2orSME2p2] in
7778
def SME2p2Unsupported : AArch64Unsupported;
7879

7980
def SME2p1Unsupported : AArch64Unsupported {

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -244,7 +244,7 @@ def HasSVEorSME
244244
: Predicate<"Subtarget->hasSVE() || (Subtarget->isStreaming() && Subtarget->hasSME())">,
245245
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME),
246246
"sve or sme">;
247-
def HasSVEorSME2p2
247+
def HasNonStreamingSVEorSME2p2
248248
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||"
249249
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())">,
250250
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2p2),
@@ -281,6 +281,11 @@ def HasSMEF16F16orSMEF8F16
281281
: Predicate<"Subtarget->isStreaming() && (Subtarget->hasSMEF16F16() || Subtarget->hasSMEF8F16())">,
282282
AssemblerPredicateWithAll<(any_of FeatureSMEF16F16, FeatureSMEF8F16),
283283
"sme-f16f16 or sme-f8f16">;
284+
def HasNonStreamingSVE2p2orSME2p2
285+
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2p2()) ||"
286+
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())">,
287+
AssemblerPredicateWithAll<(any_of FeatureSVE2p2, FeatureSME2p2),
288+
"sme2p2 or sve2p2">;
284289

285290
// A subset of NEON instructions are legal in Streaming SVE execution mode,
286291
// so don't need the additional check for 'isNeonAvailable'.

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

Lines changed: 14 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -928,9 +928,10 @@ let Predicates = [HasSVEorSME] in {
928928
defm SPLICE_ZPZ : sve_int_perm_splice<"splice", AArch64splice>;
929929
} // End HasSVEorSME
930930

931-
let Predicates = [HasSVE] in {
932-
defm COMPACT_ZPZ : sve_int_perm_compact<"compact", int_aarch64_sve_compact>;
933-
} // End HasSVE
931+
// COMPACT - word and doubleword
932+
let Predicates = [HasNonStreamingSVEorSME2p2] in {
933+
defm COMPACT_ZPZ : sve_int_perm_compact_sd<"compact", int_aarch64_sve_compact>;
934+
}
934935

935936
let Predicates = [HasSVEorSME] in {
936937
defm INSR_ZR : sve_int_perm_insrs<"insr", AArch64insr>;
@@ -4269,6 +4270,16 @@ let Predicates = [HasSVE2p2orSME2p2] in {
42694270

42704271
} // End HasSME2p2orSVE2p2
42714272

4273+
//===----------------------------------------------------------------------===//
4274+
// SME2.2 or SVE2.2 instructions - Legal in streaming mode iff target has SME2p2
4275+
//===----------------------------------------------------------------------===//
4276+
let Predicates = [HasNonStreamingSVE2p2orSME2p2] in {
4277+
// SVE2 EXPAND
4278+
defm EXPAND_ZPZ : sve2_int_perm_expand<"expand">;
4279+
// SVE COMPACT - byte and halfword
4280+
defm COMPACT_ZPZ : sve_int_perm_compact_bh<"compact">;
4281+
}
4282+
42724283
//===----------------------------------------------------------------------===//
42734284
// SVE2 FP8 instructions
42744285
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/SVEInstrFormats.td‎

Lines changed: 37 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -7252,6 +7252,32 @@ multiclass sve2_int_perm_splice_cons<string asm> {
72527252
def _D : sve2_int_perm_splice_cons<0b11, asm, ZPR64, ZZ_d>;
72537253
}
72547254

7255+
class sve2_int_perm_expand<bits<2> sz, string asm,
7256+
ZPRRegOp zprty>
7257+
: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn),
7258+
asm, "\t$Zd, $Pg, $Zn",
7259+
"",
7260+
[]>, Sched<[]> {
7261+
bits<3> Pg;
7262+
bits<5> Zn;
7263+
bits<5> Zd;
7264+
let Inst{31-24} = 0b00000101;
7265+
let Inst{23-22} = sz;
7266+
let Inst{21-13} = 0b110001100;
7267+
let Inst{12-10} = Pg;
7268+
let Inst{9-5} = Zn;
7269+
let Inst{4-0} = Zd;
7270+
7271+
let hasSideEffects = 0;
7272+
}
7273+
7274+
multiclass sve2_int_perm_expand<string asm> {
7275+
def _B : sve2_int_perm_expand<0b00, asm, ZPR8>;
7276+
def _H : sve2_int_perm_expand<0b01, asm, ZPR16>;
7277+
def _S : sve2_int_perm_expand<0b10, asm, ZPR32>;
7278+
def _D : sve2_int_perm_expand<0b11, asm, ZPR64>;
7279+
}
7280+
72557281
class sve_int_perm_rev<bits<2> sz8_64, bits<2> opc, string asm,
72567282
ZPRRegOp zprty>
72577283
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
@@ -7413,16 +7439,16 @@ multiclass sve_int_perm_cpy_v<string asm, SDPatternOperator op> {
74137439
(!cast<Instruction>(NAME # _H) $passthru, $pg, $splat)>;
74147440
}
74157441

7416-
class sve_int_perm_compact<bit sz, string asm, ZPRRegOp zprty>
7442+
class sve_int_perm_compact<bits<2> sz, string asm, ZPRRegOp zprty>
74177443
: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn),
74187444
asm, "\t$Zd, $Pg, $Zn",
74197445
"",
74207446
[]>, Sched<[]> {
74217447
bits<3> Pg;
74227448
bits<5> Zd;
74237449
bits<5> Zn;
7424-
let Inst{31-23} = 0b000001011;
7425-
let Inst{22} = sz;
7450+
let Inst{31-24} = 0b00000101;
7451+
let Inst{23-22} = sz;
74267452
let Inst{21-13} = 0b100001100;
74277453
let Inst{12-10} = Pg;
74287454
let Inst{9-5} = Zn;
@@ -7431,16 +7457,21 @@ class sve_int_perm_compact<bit sz, string asm, ZPRRegOp zprty>
74317457
let hasSideEffects = 0;
74327458
}
74337459

7434-
multiclass sve_int_perm_compact<string asm, SDPatternOperator op> {
7435-
def _S : sve_int_perm_compact<0b0, asm, ZPR32>;
7436-
def _D : sve_int_perm_compact<0b1, asm, ZPR64>;
7460+
multiclass sve_int_perm_compact_sd<string asm, SDPatternOperator op> {
7461+
def _S : sve_int_perm_compact<0b10, asm, ZPR32>;
7462+
def _D : sve_int_perm_compact<0b11, asm, ZPR64>;
74377463

74387464
def : SVE_2_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
74397465
def : SVE_2_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
74407466
def : SVE_2_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
74417467
def : SVE_2_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
74427468
}
74437469

7470+
multiclass sve_int_perm_compact_bh<string asm> {
7471+
def _B : sve_int_perm_compact<0b00, asm, ZPR8>;
7472+
def _H : sve_int_perm_compact<0b01, asm, ZPR16>;
7473+
}
7474+
74447475
//===----------------------------------------------------------------------===//
74457476
// SVE Memory - Contiguous Load Group
74467477
//===----------------------------------------------------------------------===//

‎llvm/test/MC/AArch64/SVE/compact-diagnostics.s‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,12 +28,12 @@ compact z31.s, p7, z31.d
2828
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
2929

3030
compact z31.b, p7, z31.b
31-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
31+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
3232
// CHECK-NEXT: compact z31.b, p7, z31.b
3333
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
3434

3535
compact z31.h, p7, z31.h
36-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
36+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
3737
// CHECK-NEXT: compact z31.h, p7, z31.h
3838
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
3939

‎llvm/test/MC/AArch64/SVE/compact.s‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,11 +12,11 @@
1212
compact z31.s, p7, z31.s
1313
// CHECK-INST: compact z31.s, p7, z31.s
1414
// CHECK-ENCODING: [0xff,0x9f,0xa1,0x05]
15-
// CHECK-ERROR: instruction requires: sve
15+
// CHECK-ERROR: instruction requires: sve or sme2p2
1616
// CHECK-UNKNOWN: 05a19fff <unknown>
1717

1818
compact z31.d, p7, z31.d
1919
// CHECK-INST: compact z31.d, p7, z31.d
2020
// CHECK-ENCODING: [0xff,0x9f,0xe1,0x05]
21-
// CHECK-ERROR: instruction requires: sve
21+
// CHECK-ERROR: instruction requires: sve or sme2p2
2222
// CHECK-UNKNOWN: 05e19fff <unknown>

‎llvm/test/MC/AArch64/SVE2p2/compact-diagnostics.s‎

Lines changed: 65 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,65 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
2+
3+
// --------------------------------------------------------------------------//
4+
// Invalid element widths
5+
6+
compact z31.h, p7, z31.b
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
8+
// CHECK-NEXT: compact z31.h, p7, z31.b
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
compact z31.b, p7, z31.h
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
13+
// CHECK-NEXT: compact z31.b, p7, z31.h
14+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15+
16+
// --------------------------------------------------------------------------//
17+
// Invalid predicate operation
18+
19+
compact z23.b, p7/m, z13.b
20+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
21+
// CHECK-NEXT: compact z23.b, p7/m, z13.b
22+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23+
24+
compact z23.b, p7.b, z13.b
25+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
26+
// CHECK-NEXT: compact z23.b, p7.b, z13.b
27+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
28+
29+
compact z23.h, p7/z, z13.h
30+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
31+
// CHECK-NEXT: compact z23.h, p7/z, z13.h
32+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
33+
34+
compact z23.h, p7.h, z13.h
35+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
36+
// CHECK-NEXT: compact z23.h, p7.h, z13.h
37+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
38+
39+
// --------------------------------------------------------------------------//
40+
// Predicate not in restricted predicate range
41+
42+
compact z23.b, p8, z13.b
43+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
44+
// CHECK-NEXT: compact z23.b, p8, z13.b
45+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
46+
47+
compact z23.h, p8, z13.h
48+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
49+
// CHECK-NEXT: compact z23.h, p8, z13.h
50+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
51+
52+
// --------------------------------------------------------------------------//
53+
// Negative tests for instructions that are incompatible with movprfx
54+
55+
movprfx z31.b, p7/z, z6.b
56+
compact z31.b, p7, z31.b
57+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
58+
// CHECK-NEXT: compact z31.b, p7, z31.b
59+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
60+
61+
movprfx z31, z6
62+
compact z31.h, p7, z31.h
63+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
64+
// CHECK-NEXT: compact z31.h, p7, z31.h
65+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p2/compact.s‎

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
4+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
8+
// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
9+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
10+
// RUN: | llvm-objdump -d --mattr=-sve2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
11+
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
12+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
13+
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
14+
// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
15+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
16+
17+
compact z0.b, p0, z0.b // 00000101-00100001-10000000-00000000
18+
// CHECK-INST: compact z0.b, p0, z0.b
19+
// CHECK-ENCODING: [0x00,0x80,0x21,0x05]
20+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
21+
// CHECK-UNKNOWN: 05218000 <unknown>
22+
23+
compact z21.b, p5, z10.b // 00000101-00100001-10010101-01010101
24+
// CHECK-INST: compact z21.b, p5, z10.b
25+
// CHECK-ENCODING: [0x55,0x95,0x21,0x05]
26+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
27+
// CHECK-UNKNOWN: 05219555 <unknown>
28+
29+
compact z31.h, p7, z31.h // 00000101-01100001-10011111-11111111
30+
// CHECK-INST: compact z31.h, p7, z31.h
31+
// CHECK-ENCODING: [0xff,0x9f,0x61,0x05]
32+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
33+
// CHECK-UNKNOWN: 05619fff <unknown>

‎llvm/test/MC/AArch64/SVE2p2/expand-diagnostics.s‎

Lines changed: 120 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,120 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
2+
3+
// ------------------------------------------------------------------------- //
4+
// Invalid element widths.
5+
6+
expand z23.b, p3, z13.d
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
8+
// CHECK-NEXT: expand z23.b, p3, z13.d
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
expand z23.h, p3, z13.b
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
13+
// CHECK-NEXT: expand z23.h, p3, z13.b
14+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15+
16+
expand z23.s, p3, z13.h
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
18+
// CHECK-NEXT: expand z23.s, p3, z13.h
19+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20+
21+
expand z23.d, p3, z13.s
22+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
23+
// CHECK-NEXT: expand z23.d, p3, z13.s
24+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25+
26+
expand z23.q, p3, z13.q
27+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
28+
// CHECK-NEXT: expand z23.q, p3, z13.q
29+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
30+
31+
// --------------------------------------------------------------------------//
32+
// Invalid predicate operation
33+
34+
expand z23.b, p3/z, z13.b
35+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
36+
// CHECK-NEXT: expand z23.b, p3/z, z13.b
37+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
38+
39+
expand z23.b, p3.b, z13.b
40+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
41+
// CHECK-NEXT: expand z23.b, p3.b, z13.b
42+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
43+
44+
expand z23.h, p3/m, z13.h
45+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
46+
// CHECK-NEXT: expand z23.h, p3/m, z13.h
47+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
48+
49+
expand z23.h, p3.h, z13.h
50+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
51+
// CHECK-NEXT: expand z23.h, p3.h, z13.h
52+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
53+
54+
expand z23.s, p3/z, z13.s
55+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
56+
// CHECK-NEXT: expand z23.s, p3/z, z13.s
57+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
58+
59+
expand z23.s, p3.s, z13.s
60+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
61+
// CHECK-NEXT: expand z23.s, p3.s, z13.s
62+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
63+
64+
expand z23.d, p3/m, z13.d
65+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
66+
// CHECK-NEXT: expand z23.d, p3/m, z13.d
67+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
68+
69+
expand z23.d, p3.d, z13.d
70+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
71+
// CHECK-NEXT: expand z23.d, p3.d, z13.d
72+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
73+
74+
// --------------------------------------------------------------------------//
75+
// Predicate not in restricted predicate range
76+
77+
expand z23.b, p8, z13.b
78+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
79+
// CHECK-NEXT: expand z23.b, p8, z13.b
80+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
81+
82+
expand z23.b, p3.b, z13.b
83+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
84+
// CHECK-NEXT: expand z23.b, p3.b, z13.b
85+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
86+
87+
expand z23.h, p8, z13.h
88+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
89+
// CHECK-NEXT: expand z23.h, p8, z13.h
90+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
91+
92+
expand z23.h, p3.h, z13.h
93+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
94+
// CHECK-NEXT: expand z23.h, p3.h, z13.h
95+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}
96+
97+
expand z23.s, p8, z13.s
98+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
99+
// CHECK-NEXT: expand z23.s, p8, z13.s
100+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
101+
102+
expand z23.d, p8, z13.d
103+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
104+
// CHECK-NEXT: expand z23.d, p8, z13.d
105+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
106+
107+
// --------------------------------------------------------------------------//
108+
// Negative tests for instructions that are incompatible with movprfx
109+
110+
movprfx z31, z6
111+
expand z31.b, p7, z31.b
112+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
113+
// CHECK-NEXT: expand z31.b, p7, z31.b
114+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
115+
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movprfx z31.b, p0/z, z6.b
117+
expand z31.b, p0, z31.b
118+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
119+
// CHECK-NEXT: expand z31.b, p0, z31.b
120+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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