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sdesmalen-armsdesmalen-arm
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Use Windows-style prologue/epilogue even without CFI
1 parent 549330a commit e9c0090

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7 files changed

+135
-133
lines changed

7 files changed

+135
-133
lines changed

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp‎

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -373,8 +373,7 @@ static bool isTargetWindows(const MachineFunction &MF) {
373373
// We could consider rearranging the spills for simpler cases.
374374
static bool hasSVECalleeSavesAboveFrameRecord(const MachineFunction &MF) {
375375
auto *AFI = MF.getInfo<AArch64FunctionInfo>();
376-
return isTargetWindows(MF) && AFI->getSVECalleeSavedStackSize() &&
377-
needsWinCFI(MF);
376+
return isTargetWindows(MF) && AFI->getSVECalleeSavedStackSize();
378377
}
379378

380379
/// Returns true if a homogeneous prolog or epilog code can be emitted
@@ -390,7 +389,7 @@ bool AArch64FrameLowering::homogeneousPrologEpilog(
390389
return false;
391390

392391
// TODO: Window is supported yet.
393-
if (needsWinCFI(MF))
392+
if (isTargetWindows(MF))
394393
return false;
395394

396395
// TODO: SVE is not supported yet.
@@ -1251,7 +1250,7 @@ bool AArch64FrameLowering::shouldCombineCSRLocalStackBump(
12511250
// unwind format for functions that both have a local area and callee saved
12521251
// registers. Using the packed unwind format notably reduces the size of
12531252
// the unwind info.
1254-
if (needsWinCFI(MF) && AFI->getCalleeSavedStackSize() > 0 &&
1253+
if (isTargetWindows(MF) && AFI->getCalleeSavedStackSize() > 0 &&
12551254
MF.getFunction().hasOptSize())
12561255
return false;
12571256

@@ -3254,7 +3253,6 @@ static void computeCalleeSaveRegisterPairs(
32543253
return;
32553254

32563255
bool IsWindows = isTargetWindows(MF);
3257-
bool NeedsWinCFI = needsWinCFI(MF);
32583256
AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
32593257
unsigned StackHazardSize = getStackHazardSize(MF);
32603258
MachineFrameInfo &MFI = MF.getFrameInfo();
@@ -3271,7 +3269,7 @@ static void computeCalleeSaveRegisterPairs(
32713269
int StackFillDir = -1;
32723270
int RegInc = 1;
32733271
unsigned FirstReg = 0;
3274-
if (NeedsWinCFI) {
3272+
if (IsWindows) {
32753273
// For WinCFI, fill the stack from the bottom up.
32763274
ByteOffset = 0;
32773275
StackFillDir = 1;
@@ -3280,9 +3278,9 @@ static void computeCalleeSaveRegisterPairs(
32803278
RegInc = -1;
32813279
FirstReg = Count - 1;
32823280
}
3283-
bool FPAfterSVECalleeSaves = hasSVECalleeSavesAboveFrameRecord(MF);
3284-
int ScalableByteOffset =
3285-
FPAfterSVECalleeSaves ? 0 : AFI->getSVECalleeSavedStackSize();
3281+
int ScalableByteOffset = hasSVECalleeSavesAboveFrameRecord(MF)
3282+
? 0
3283+
: AFI->getSVECalleeSavedStackSize();
32863284
bool NeedGapToAlignStack = AFI->hasCalleeSaveStackFreeSpace();
32873285
Register LastReg = 0;
32883286

@@ -3320,6 +3318,7 @@ static void computeCalleeSaveRegisterPairs(
33203318
ByteOffset += StackFillDir * StackHazardSize;
33213319
LastReg = RPI.Reg1;
33223320

3321+
bool NeedsWinCFI = needsWinCFI(MF);
33233322
int Scale = TRI->getSpillSize(*RPI.RC);
33243323
// Add the next reg to the pair if it is in the same register class.
33253324
if (unsigned(i + RegInc) < Count && !AFI->hasStackHazardSlotIndex()) {
@@ -3335,8 +3334,9 @@ static void computeCalleeSaveRegisterPairs(
33353334
break;
33363335
case RegPairInfo::FPR64:
33373336
if (AArch64::FPR64RegClass.contains(NextReg) &&
3338-
!invalidateWindowsRegisterPairing(RPI.Reg1, NextReg, NeedsWinCFI,
3339-
IsFirst, TRI))
3337+
!invalidateRegisterPairing(
3338+
RPI.Reg1, NextReg, IsWindows, NeedsWinCFI,
3339+
/*NeedsFrameRecord=*/false, IsFirst, TRI))
33403340
RPI.Reg2 = NextReg;
33413341
break;
33423342
case RegPairInfo::FPR128:
@@ -3390,7 +3390,7 @@ static void computeCalleeSaveRegisterPairs(
33903390
"Callee-save registers not saved as adjacent register pair!");
33913391

33923392
RPI.FrameIdx = CSI[i].getFrameIdx();
3393-
if (NeedsWinCFI &&
3393+
if (IsWindows &&
33943394
RPI.isPaired()) // RPI.FrameIdx must be the lower index of the pair
33953395
RPI.FrameIdx = CSI[i + RegInc].getFrameIdx();
33963396

@@ -3417,7 +3417,7 @@ static void computeCalleeSaveRegisterPairs(
34173417

34183418
// Round up size of non-pair to pair size if we need to pad the
34193419
// callee-save area to ensure 16-byte alignment.
3420-
if (NeedGapToAlignStack && !NeedsWinCFI && !RPI.isScalable() &&
3420+
if (NeedGapToAlignStack && !IsWindows && !RPI.isScalable() &&
34213421
RPI.Type != RegPairInfo::FPR128 && !RPI.isPaired() &&
34223422
ByteOffset % 16 != 0) {
34233423
ByteOffset += 8 * StackFillDir;
@@ -3433,7 +3433,7 @@ static void computeCalleeSaveRegisterPairs(
34333433
assert(OffsetPost % Scale == 0);
34343434
// If filling top down (default), we want the offset after incrementing it.
34353435
// If filling bottom up (WinCFI) we need the original offset.
3436-
int Offset = NeedsWinCFI ? OffsetPre : OffsetPost;
3436+
int Offset = IsWindows ? OffsetPre : OffsetPost;
34373437

34383438
// The FP, LR pair goes 8 bytes into our expanded 24-byte slot so that the
34393439
// Swift context can directly precede FP.
@@ -3472,7 +3472,7 @@ static void computeCalleeSaveRegisterPairs(
34723472
if (RPI.isPaired())
34733473
i += RegInc;
34743474
}
3475-
if (NeedsWinCFI) {
3475+
if (IsWindows) {
34763476
// If we need an alignment gap in the stack, align the topmost stack
34773477
// object. A stack frame with a gap looks like this, bottom up:
34783478
// x19, d8. d9, gap.
@@ -3607,14 +3607,15 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
36073607
if (RPI.isPaired()) dbgs() << ", " << RPI.FrameIdx + 1;
36083608
dbgs() << ")\n");
36093609

3610-
assert((!NeedsWinCFI || !(Reg1 == AArch64::LR && Reg2 == AArch64::FP)) &&
3610+
assert((!isTargetWindows(MF) ||
3611+
!(Reg1 == AArch64::LR && Reg2 == AArch64::FP)) &&
36113612
"Windows unwdinding requires a consecutive (FP,LR) pair");
36123613
// Windows unwind codes require consecutive registers if registers are
36133614
// paired. Make the switch here, so that the code below will save (x,x+1)
36143615
// and not (x+1,x).
36153616
unsigned FrameIdxReg1 = RPI.FrameIdx;
36163617
unsigned FrameIdxReg2 = RPI.FrameIdx + 1;
3617-
if (NeedsWinCFI && RPI.isPaired()) {
3618+
if (isTargetWindows(MF) && RPI.isPaired()) {
36183619
std::swap(Reg1, Reg2);
36193620
std::swap(FrameIdxReg1, FrameIdxReg2);
36203621
}
@@ -3776,7 +3777,7 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
37763777
// and not (x+1,x).
37773778
unsigned FrameIdxReg1 = RPI.FrameIdx;
37783779
unsigned FrameIdxReg2 = RPI.FrameIdx + 1;
3779-
if (NeedsWinCFI && RPI.isPaired()) {
3780+
if (isTargetWindows(MF) && RPI.isPaired()) {
37803781
std::swap(Reg1, Reg2);
37813782
std::swap(FrameIdxReg1, FrameIdxReg2);
37823783
}
@@ -4192,14 +4193,14 @@ bool AArch64FrameLowering::assignCalleeSavedSpillSlots(
41924193
MachineFunction &MF, const TargetRegisterInfo *RegInfo,
41934194
std::vector<CalleeSavedInfo> &CSI, unsigned &MinCSFrameIndex,
41944195
unsigned &MaxCSFrameIndex) const {
4195-
bool NeedsWinCFI = needsWinCFI(MF);
4196+
bool IsWindows = isTargetWindows(MF);
41964197
unsigned StackHazardSize = getStackHazardSize(MF);
41974198
// To match the canonical windows frame layout, reverse the list of
41984199
// callee saved registers to get them laid out by PrologEpilogInserter
41994200
// in the right order. (PrologEpilogInserter allocates stack objects top
42004201
// down. Windows canonical prologs store higher numbered registers at
42014202
// the top, thus have the CSI array start from the highest registers.)
4202-
if (NeedsWinCFI)
4203+
if (IsWindows)
42034204
std::reverse(CSI.begin(), CSI.end());
42044205

42054206
if (CSI.empty())
@@ -4210,8 +4211,7 @@ bool AArch64FrameLowering::assignCalleeSavedSpillSlots(
42104211
MachineFrameInfo &MFI = MF.getFrameInfo();
42114212
auto *AFI = MF.getInfo<AArch64FunctionInfo>();
42124213

4213-
bool UsesWinAAPCS = isTargetWindows(MF);
4214-
if (UsesWinAAPCS && hasFP(MF) && AFI->hasSwiftAsyncContext()) {
4214+
if (IsWindows && hasFP(MF) && AFI->hasSwiftAsyncContext()) {
42154215
int FrameIdx = MFI.CreateStackObject(8, Align(16), true);
42164216
AFI->setSwiftAsyncContextFrameIdx(FrameIdx);
42174217
if ((unsigned)FrameIdx < MinCSFrameIndex)
@@ -4264,7 +4264,7 @@ bool AArch64FrameLowering::assignCalleeSavedSpillSlots(
42644264
MaxCSFrameIndex = FrameIdx;
42654265

42664266
// Grab 8 bytes below FP for the extended asynchronous frame info.
4267-
if (hasFP(MF) && AFI->hasSwiftAsyncContext() && !UsesWinAAPCS &&
4267+
if (hasFP(MF) && AFI->hasSwiftAsyncContext() && !IsWindows &&
42684268
Reg == AArch64::FP) {
42694269
FrameIdx = MFI.CreateStackObject(8, Alignment, true);
42704270
AFI->setSwiftAsyncContextFrameIdx(FrameIdx);

‎llvm/test/CodeGen/AArch64/arm64ec-reservedregs.ll‎

Lines changed: 38 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -9,20 +9,20 @@
99
define i32 @no_int_regs(i32 %x) nounwind {
1010
; CHECK-LABEL: no_int_regs:
1111
; CHECK: // %bb.0: // %entry
12-
; CHECK-NEXT: stp x30, x29, [sp, #-80]! // 16-byte Folded Spill
13-
; CHECK-NEXT: str x27, [sp, #16] // 8-byte Folded Spill
14-
; CHECK-NEXT: stp x26, x25, [sp, #32] // 16-byte Folded Spill
15-
; CHECK-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
16-
; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
17-
; CHECK-NEXT: str w0, [sp, #28] // 4-byte Folded Spill
12+
; CHECK-NEXT: stp x19, x20, [sp, #-80]! // 16-byte Folded Spill
13+
; CHECK-NEXT: stp x21, x22, [sp, #16] // 16-byte Folded Spill
14+
; CHECK-NEXT: stp x25, x26, [sp, #32] // 16-byte Folded Spill
15+
; CHECK-NEXT: str x27, [sp, #48] // 8-byte Folded Spill
16+
; CHECK-NEXT: stp x29, x30, [sp, #56] // 16-byte Folded Spill
17+
; CHECK-NEXT: str w0, [sp, #76] // 4-byte Folded Spill
1818
; CHECK-NEXT: //APP
1919
; CHECK-NEXT: //NO_APP
20-
; CHECK-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
21-
; CHECK-NEXT: ldr w0, [sp, #28] // 4-byte Folded Reload
22-
; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
23-
; CHECK-NEXT: ldr x27, [sp, #16] // 8-byte Folded Reload
24-
; CHECK-NEXT: ldp x26, x25, [sp, #32] // 16-byte Folded Reload
25-
; CHECK-NEXT: ldp x30, x29, [sp], #80 // 16-byte Folded Reload
20+
; CHECK-NEXT: ldp x29, x30, [sp, #56] // 16-byte Folded Reload
21+
; CHECK-NEXT: ldr w0, [sp, #76] // 4-byte Folded Reload
22+
; CHECK-NEXT: ldp x25, x26, [sp, #32] // 16-byte Folded Reload
23+
; CHECK-NEXT: ldr x27, [sp, #48] // 8-byte Folded Reload
24+
; CHECK-NEXT: ldp x21, x22, [sp, #16] // 16-byte Folded Reload
25+
; CHECK-NEXT: ldp x19, x20, [sp], #80 // 16-byte Folded Reload
2626
; CHECK-NEXT: ret
2727
entry:
2828
tail call void asm sideeffect "", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x15},~{x16},~{x17},~{x19},~{x20},~{x21},~{x22},~{x25},~{x26},~{x27},~{fp},~{lr}"()
@@ -32,20 +32,20 @@ entry:
3232
define i32 @one_int_reg(i32 %x) nounwind {
3333
; CHECK-LABEL: one_int_reg:
3434
; CHECK: // %bb.0: // %entry
35-
; CHECK-NEXT: stp x30, x29, [sp, #-80]! // 16-byte Folded Spill
36-
; CHECK-NEXT: str x27, [sp, #16] // 8-byte Folded Spill
35+
; CHECK-NEXT: stp x19, x20, [sp, #-80]! // 16-byte Folded Spill
36+
; CHECK-NEXT: stp x21, x22, [sp, #16] // 16-byte Folded Spill
37+
; CHECK-NEXT: stp x25, x26, [sp, #32] // 16-byte Folded Spill
38+
; CHECK-NEXT: str x27, [sp, #48] // 8-byte Folded Spill
39+
; CHECK-NEXT: stp x29, x30, [sp, #56] // 16-byte Folded Spill
3740
; CHECK-NEXT: mov w30, w0
38-
; CHECK-NEXT: stp x26, x25, [sp, #32] // 16-byte Folded Spill
39-
; CHECK-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill
40-
; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
4141
; CHECK-NEXT: //APP
4242
; CHECK-NEXT: //NO_APP
43-
; CHECK-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
44-
; CHECK-NEXT: ldr x27, [sp, #16] // 8-byte Folded Reload
45-
; CHECK-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload
4643
; CHECK-NEXT: mov w0, w30
47-
; CHECK-NEXT: ldp x26, x25, [sp, #32] // 16-byte Folded Reload
48-
; CHECK-NEXT: ldp x30, x29, [sp], #80 // 16-byte Folded Reload
44+
; CHECK-NEXT: ldp x29, x30, [sp, #56] // 16-byte Folded Reload
45+
; CHECK-NEXT: ldp x25, x26, [sp, #32] // 16-byte Folded Reload
46+
; CHECK-NEXT: ldr x27, [sp, #48] // 8-byte Folded Reload
47+
; CHECK-NEXT: ldp x21, x22, [sp, #16] // 16-byte Folded Reload
48+
; CHECK-NEXT: ldp x19, x20, [sp], #80 // 16-byte Folded Reload
4949
; CHECK-NEXT: ret
5050
entry:
5151
tail call void asm sideeffect "", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x15},~{x16},~{x17},~{x19},~{x20},~{x21},~{x22},~{x25},~{x26},~{x27},~{fp}"()
@@ -56,18 +56,18 @@ define float @no_float_regs(float %x) nounwind {
5656
; CHECK-LABEL: no_float_regs:
5757
; CHECK: // %bb.0: // %entry
5858
; CHECK-NEXT: sub sp, sp, #80
59-
; CHECK-NEXT: stp d15, d14, [sp, #16] // 16-byte Folded Spill
60-
; CHECK-NEXT: stp d13, d12, [sp, #32] // 16-byte Folded Spill
61-
; CHECK-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill
62-
; CHECK-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill
59+
; CHECK-NEXT: stp d8, d9, [sp, #16] // 16-byte Folded Spill
60+
; CHECK-NEXT: stp d10, d11, [sp, #32] // 16-byte Folded Spill
61+
; CHECK-NEXT: stp d12, d13, [sp, #48] // 16-byte Folded Spill
62+
; CHECK-NEXT: stp d14, d15, [sp, #64] // 16-byte Folded Spill
6363
; CHECK-NEXT: str s0, [sp, #12] // 4-byte Folded Spill
6464
; CHECK-NEXT: //APP
6565
; CHECK-NEXT: //NO_APP
66-
; CHECK-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
66+
; CHECK-NEXT: ldp d14, d15, [sp, #64] // 16-byte Folded Reload
6767
; CHECK-NEXT: ldr s0, [sp, #12] // 4-byte Folded Reload
68-
; CHECK-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
69-
; CHECK-NEXT: ldp d13, d12, [sp, #32] // 16-byte Folded Reload
70-
; CHECK-NEXT: ldp d15, d14, [sp, #16] // 16-byte Folded Reload
68+
; CHECK-NEXT: ldp d12, d13, [sp, #48] // 16-byte Folded Reload
69+
; CHECK-NEXT: ldp d10, d11, [sp, #32] // 16-byte Folded Reload
70+
; CHECK-NEXT: ldp d8, d9, [sp, #16] // 16-byte Folded Reload
7171
; CHECK-NEXT: add sp, sp, #80
7272
; CHECK-NEXT: ret
7373
entry:
@@ -78,18 +78,18 @@ entry:
7878
define float @one_float_reg(float %x) nounwind {
7979
; CHECK-LABEL: one_float_reg:
8080
; CHECK: // %bb.0: // %entry
81-
; CHECK-NEXT: stp d15, d14, [sp, #-64]! // 16-byte Folded Spill
81+
; CHECK-NEXT: stp d8, d9, [sp, #-64]! // 16-byte Folded Spill
82+
; CHECK-NEXT: stp d14, d15, [sp, #48] // 16-byte Folded Spill
8283
; CHECK-NEXT: fmov s15, s0
83-
; CHECK-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill
84-
; CHECK-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill
85-
; CHECK-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill
84+
; CHECK-NEXT: stp d10, d11, [sp, #16] // 16-byte Folded Spill
85+
; CHECK-NEXT: stp d12, d13, [sp, #32] // 16-byte Folded Spill
8686
; CHECK-NEXT: //APP
8787
; CHECK-NEXT: //NO_APP
88-
; CHECK-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
89-
; CHECK-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
88+
; CHECK-NEXT: ldp d12, d13, [sp, #32] // 16-byte Folded Reload
9089
; CHECK-NEXT: fmov s0, s15
91-
; CHECK-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload
92-
; CHECK-NEXT: ldp d15, d14, [sp], #64 // 16-byte Folded Reload
90+
; CHECK-NEXT: ldp d14, d15, [sp, #48] // 16-byte Folded Reload
91+
; CHECK-NEXT: ldp d10, d11, [sp, #16] // 16-byte Folded Reload
92+
; CHECK-NEXT: ldp d8, d9, [sp], #64 // 16-byte Folded Reload
9393
; CHECK-NEXT: ret
9494
entry:
9595
tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14}"()

‎llvm/test/CodeGen/AArch64/framelayout-sve-win.mir‎

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -900,19 +900,20 @@ body: |
900900
bb.0.entry:
901901
; CHECK-LABEL: name: test_nounwind_layout
902902
; CHECK: fixedStack:
903-
; CHECK: liveins: $x20, $lr, $z8, $p8
903+
; CHECK: liveins: $p8, $z8, $lr, $x20
904904
; CHECK-NEXT: {{ $}}
905-
; CHECK-NEXT: early-clobber $sp = frame-setup STPXpre killed $lr, killed $x20, $sp, -2 :: (store (s64) into %stack.3), (store (s64) into %stack.2)
906905
; CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -2, implicit $vg
907-
; CHECK-NEXT: frame-setup STR_ZXI killed $z8, $sp, 1 :: (store (s128) into %stack.1)
908-
; CHECK-NEXT: frame-setup STR_PXI killed $p8, $sp, 15 :: (store (s16) into %stack.0)
906+
; CHECK-NEXT: frame-setup STR_PXI killed $p8, $sp, 0 :: (store (s16) into %stack.3)
907+
; CHECK-NEXT: frame-setup STR_ZXI killed $z8, $sp, 1 :: (store (s128) into %stack.2)
908+
; CHECK-NEXT: early-clobber $sp = frame-setup STPXpre killed $x20, killed $lr, $sp, -2 :: (store (s64) into %stack.0), (store (s64) into %stack.1)
909909
; CHECK-NEXT: $x20 = IMPLICIT_DEF
910910
; CHECK-NEXT: $p8 = IMPLICIT_DEF
911911
; CHECK-NEXT: $z8 = IMPLICIT_DEF
912-
; CHECK-NEXT: $p8 = frame-destroy LDR_PXI $sp, 15 :: (load (s16) from %stack.0)
913-
; CHECK-NEXT: $z8 = frame-destroy LDR_ZXI $sp, 1 :: (load (s128) from %stack.1)
912+
; CHECK-NEXT: $x20, $lr = frame-destroy LDPXi $sp, 0 :: (load (s64) from %stack.0), (load (s64) from %stack.1)
913+
; CHECK-NEXT: $sp = frame-destroy ADDXri $sp, 16, 0
914+
; CHECK-NEXT: $z8 = frame-destroy LDR_ZXI $sp, 1 :: (load (s128) from %stack.2)
915+
; CHECK-NEXT: $p8 = frame-destroy LDR_PXI $sp, 0 :: (load (s16) from %stack.3)
914916
; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 2, implicit $vg
915-
; CHECK-NEXT: early-clobber $sp, $lr, $x20 = frame-destroy LDPXpost $sp, 2 :: (load (s64) from %stack.3), (load (s64) from %stack.2)
916917
; CHECK-NEXT: RET_ReallyLR
917918
$x20 = IMPLICIT_DEF
918919
$p8 = IMPLICIT_DEF

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