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ParkHanbumParkHanbum
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add testcases for upcoming patch
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‎llvm/test/Transforms/VectorCombine/load-insert-store.ll‎

Lines changed: 318 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,71 @@ entry:
1616
ret void
1717
}
1818

19+
define void @insert_store2(ptr %q, i16 zeroext %s) {
20+
; CHECK-LABEL: @insert_store2(
21+
; CHECK-NEXT: entry:
22+
; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr [[Q:%.*]], align 16
23+
; CHECK-NEXT: [[VEC1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[S:%.*]], i32 6
24+
; CHECK-NEXT: [[VEC2:%.*]] = insertelement <8 x i16> [[VEC1]], i16 [[S]], i32 7
25+
; CHECK-NEXT: store <8 x i16> [[VEC2]], ptr [[Q]], align 1
26+
; CHECK-NEXT: ret void
27+
;
28+
entry:
29+
%0 = load <8 x i16>, ptr %q
30+
%vec1 = insertelement <8 x i16> %0, i16 %s, i32 6
31+
%vec2 = insertelement <8 x i16> %vec1, i16 %s, i32 7
32+
store <8 x i16> %vec2, ptr %q, align 1
33+
ret void
34+
}
35+
36+
define void @insert_store3(ptr %q, i16 zeroext %s) {
37+
; CHECK-LABEL: @insert_store3(
38+
; CHECK-NEXT: entry:
39+
; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr [[Q:%.*]], align 16
40+
; CHECK-NEXT: [[VEC1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[S:%.*]], i32 5
41+
; CHECK-NEXT: [[VEC2:%.*]] = insertelement <8 x i16> [[VEC1]], i16 [[S]], i32 6
42+
; CHECK-NEXT: [[VEC3:%.*]] = insertelement <8 x i16> [[VEC2]], i16 [[S]], i32 7
43+
; CHECK-NEXT: store <8 x i16> [[VEC3]], ptr [[Q]], align 1
44+
; CHECK-NEXT: ret void
45+
;
46+
entry:
47+
%0 = load <8 x i16>, ptr %q
48+
%vec1 = insertelement <8 x i16> %0, i16 %s, i32 5
49+
%vec2 = insertelement <8 x i16> %vec1, i16 %s, i32 6
50+
%vec3 = insertelement <8 x i16> %vec2, i16 %s, i32 7
51+
store <8 x i16> %vec3, ptr %q, align 1
52+
ret void
53+
}
54+
55+
define void @insert_store8(ptr %q, i16 zeroext %s) {
56+
; CHECK-LABEL: @insert_store8(
57+
; CHECK-NEXT: entry:
58+
; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr [[Q:%.*]], align 16
59+
; CHECK-NEXT: [[VEC1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[S:%.*]], i32 0
60+
; CHECK-NEXT: [[VEC2:%.*]] = insertelement <8 x i16> [[VEC1]], i16 [[S]], i32 1
61+
; CHECK-NEXT: [[VEC3:%.*]] = insertelement <8 x i16> [[VEC2]], i16 [[S]], i32 2
62+
; CHECK-NEXT: [[VEC4:%.*]] = insertelement <8 x i16> [[VEC3]], i16 [[S]], i32 3
63+
; CHECK-NEXT: [[VEC5:%.*]] = insertelement <8 x i16> [[VEC4]], i16 [[S]], i32 4
64+
; CHECK-NEXT: [[VEC6:%.*]] = insertelement <8 x i16> [[VEC5]], i16 [[S]], i32 5
65+
; CHECK-NEXT: [[VEC7:%.*]] = insertelement <8 x i16> [[VEC6]], i16 [[S]], i32 6
66+
; CHECK-NEXT: [[VEC8:%.*]] = insertelement <8 x i16> [[VEC7]], i16 [[S]], i32 7
67+
; CHECK-NEXT: store <8 x i16> [[VEC8]], ptr [[Q]], align 1
68+
; CHECK-NEXT: ret void
69+
;
70+
entry:
71+
%0 = load <8 x i16>, ptr %q
72+
%vec1 = insertelement <8 x i16> %0, i16 %s, i32 0
73+
%vec2 = insertelement <8 x i16> %vec1, i16 %s, i32 1
74+
%vec3 = insertelement <8 x i16> %vec2, i16 %s, i32 2
75+
%vec4 = insertelement <8 x i16> %vec3, i16 %s, i32 3
76+
%vec5 = insertelement <8 x i16> %vec4, i16 %s, i32 4
77+
%vec6 = insertelement <8 x i16> %vec5, i16 %s, i32 5
78+
%vec7 = insertelement <8 x i16> %vec6, i16 %s, i32 6
79+
%vec8 = insertelement <8 x i16> %vec7, i16 %s, i32 7
80+
store <8 x i16> %vec8, ptr %q, align 1
81+
ret void
82+
}
83+
1984
define void @insert_store_i16_align1(ptr %q, i16 zeroext %s) {
2085
; CHECK-LABEL: @insert_store_i16_align1(
2186
; CHECK-NEXT: entry:
@@ -827,3 +892,256 @@ bb:
827892

828893
declare i32 @bar(i32, i1) readonly
829894
declare double @llvm.log2.f64(double)
895+
896+
define void @insert_store_gap(ptr %q, i16 zeroext %s) {
897+
; CHECK-LABEL: @insert_store_gap(
898+
; CHECK-NEXT: entry:
899+
; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr [[Q:%.*]], align 16
900+
; CHECK-NEXT: [[VEC1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[S:%.*]], i32 2
901+
; CHECK-NEXT: [[VEC2:%.*]] = insertelement <8 x i16> [[VEC1]], i16 [[S]], i32 5
902+
; CHECK-NEXT: store <8 x i16> [[VEC2]], ptr [[Q]], align 16
903+
; CHECK-NEXT: ret void
904+
;
905+
entry:
906+
%0 = load <8 x i16>, ptr %q
907+
%vec1 = insertelement <8 x i16> %0, i16 %s, i32 2
908+
%vec2 = insertelement <8 x i16> %vec1, i16 %s, i32 5
909+
store <8 x i16> %vec2, ptr %q
910+
ret void
911+
}
912+
913+
define void @insert_store_reverse(ptr %q, i16 zeroext %s) {
914+
; CHECK-LABEL: @insert_store_reverse(
915+
; CHECK-NEXT: entry:
916+
; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr [[Q:%.*]], align 16
917+
; CHECK-NEXT: [[VEC1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[S:%.*]], i32 7
918+
; CHECK-NEXT: [[VEC2:%.*]] = insertelement <8 x i16> [[VEC1]], i16 [[S]], i32 6
919+
; CHECK-NEXT: [[VEC3:%.*]] = insertelement <8 x i16> [[VEC2]], i16 [[S]], i32 5
920+
; CHECK-NEXT: store <8 x i16> [[VEC3]], ptr [[Q]], align 16
921+
; CHECK-NEXT: ret void
922+
;
923+
entry:
924+
%0 = load <8 x i16>, ptr %q
925+
%vec1 = insertelement <8 x i16> %0, i16 %s, i32 7
926+
%vec2 = insertelement <8 x i16> %vec1, i16 %s, i32 6
927+
%vec3 = insertelement <8 x i16> %vec2, i16 %s, i32 5
928+
store <8 x i16> %vec3, ptr %q
929+
ret void
930+
}
931+
932+
define void @insert_store_duplicate(ptr %q, i16 zeroext %s) {
933+
; CHECK-LABEL: @insert_store_duplicate(
934+
; CHECK-NEXT: entry:
935+
; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr [[Q:%.*]], align 16
936+
; CHECK-NEXT: [[VEC1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[S:%.*]], i32 3
937+
; CHECK-NEXT: [[VEC2:%.*]] = insertelement <8 x i16> [[VEC1]], i16 [[S]], i32 3
938+
; CHECK-NEXT: store <8 x i16> [[VEC2]], ptr [[Q]], align 16
939+
; CHECK-NEXT: ret void
940+
;
941+
entry:
942+
%0 = load <8 x i16>, ptr %q
943+
%vec1 = insertelement <8 x i16> %0, i16 %s, i32 3
944+
%vec2 = insertelement <8 x i16> %vec1, i16 %s, i32 3
945+
store <8 x i16> %vec2, ptr %q
946+
ret void
947+
}
948+
949+
define void @insert_store_i32(ptr %q, i32 zeroext %s) {
950+
; CHECK-LABEL: @insert_store_i32(
951+
; CHECK-NEXT: entry:
952+
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[Q:%.*]], align 16
953+
; CHECK-NEXT: [[VEC1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[S:%.*]], i32 2
954+
; CHECK-NEXT: [[VEC2:%.*]] = insertelement <4 x i32> [[VEC1]], i32 [[S]], i32 3
955+
; CHECK-NEXT: store <4 x i32> [[VEC2]], ptr [[Q]], align 16
956+
; CHECK-NEXT: ret void
957+
;
958+
entry:
959+
%0 = load <4 x i32>, ptr %q
960+
%vec1 = insertelement <4 x i32> %0, i32 %s, i32 2
961+
%vec2 = insertelement <4 x i32> %vec1, i32 %s, i32 3
962+
store <4 x i32> %vec2, ptr %q
963+
ret void
964+
}
965+
966+
define void @insert_store_i8(ptr %q, i8 zeroext %s) {
967+
; CHECK-LABEL: @insert_store_i8(
968+
; CHECK-NEXT: entry:
969+
; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[Q:%.*]], align 16
970+
; CHECK-NEXT: [[VEC1:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 8
971+
; CHECK-NEXT: [[VEC2:%.*]] = insertelement <16 x i8> [[VEC1]], i8 [[S]], i32 9
972+
; CHECK-NEXT: store <16 x i8> [[VEC2]], ptr [[Q]], align 16
973+
; CHECK-NEXT: ret void
974+
;
975+
entry:
976+
%0 = load <16 x i8>, ptr %q
977+
%vec1 = insertelement <16 x i8> %0, i8 %s, i32 8
978+
%vec2 = insertelement <16 x i8> %vec1, i8 %s, i32 9
979+
store <16 x i8> %vec2, ptr %q
980+
ret void
981+
}
982+
983+
define void @insert_store_alignment(ptr %q, i16 zeroext %s) {
984+
; CHECK-LABEL: @insert_store_alignment(
985+
; CHECK-NEXT: entry:
986+
; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr [[Q:%.*]], align 16
987+
; CHECK-NEXT: [[VEC1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[S:%.*]], i32 0
988+
; CHECK-NEXT: [[VEC2:%.*]] = insertelement <8 x i16> [[VEC1]], i16 [[S]], i32 4
989+
; CHECK-NEXT: store <8 x i16> [[VEC2]], ptr [[Q]], align 16
990+
; CHECK-NEXT: ret void
991+
;
992+
entry:
993+
%0 = load <8 x i16>, ptr %q, align 16
994+
%vec1 = insertelement <8 x i16> %0, i16 %s, i32 0
995+
%vec2 = insertelement <8 x i16> %vec1, i16 %s, i32 4
996+
store <8 x i16> %vec2, ptr %q, align 16
997+
ret void
998+
}
999+
1000+
define void @insert_store_size(ptr %q, i16 zeroext %s) {
1001+
; CHECK-LABEL: @insert_store_size(
1002+
; CHECK-NEXT: entry:
1003+
; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i16>, ptr [[Q:%.*]], align 32
1004+
; CHECK-NEXT: [[VEC1:%.*]] = insertelement <16 x i16> [[TMP0]], i16 [[S:%.*]], i32 8
1005+
; CHECK-NEXT: [[VEC2:%.*]] = insertelement <16 x i16> [[VEC1]], i16 [[S]], i32 12
1006+
; CHECK-NEXT: store <16 x i16> [[VEC2]], ptr [[Q]], align 32
1007+
; CHECK-NEXT: ret void
1008+
;
1009+
entry:
1010+
%0 = load <16 x i16>, ptr %q
1011+
%vec1 = insertelement <16 x i16> %0, i16 %s, i32 8
1012+
%vec2 = insertelement <16 x i16> %vec1, i16 %s, i32 12
1013+
store <16 x i16> %vec2, ptr %q
1014+
ret void
1015+
}
1016+
1017+
define void @insert_store_nonconst4(ptr %q, i8 zeroext %s, i32 %idx1, i32 %idx2, i32 %idx3, i32 %idx4) {
1018+
; CHECK-LABEL: @insert_store_nonconst4(
1019+
; CHECK-NEXT: entry:
1020+
; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[Q:%.*]], align 16
1021+
; CHECK-NEXT: [[VECINS1:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX1:%.*]]
1022+
; CHECK-NEXT: [[VECINS2:%.*]] = insertelement <16 x i8> [[VECINS1]], i8 [[S]], i32 [[IDX2:%.*]]
1023+
; CHECK-NEXT: [[VECINS3:%.*]] = insertelement <16 x i8> [[VECINS2]], i8 [[S]], i32 [[IDX3:%.*]]
1024+
; CHECK-NEXT: [[VECINS4:%.*]] = insertelement <16 x i8> [[VECINS3]], i8 [[S]], i32 [[IDX4:%.*]]
1025+
; CHECK-NEXT: store <16 x i8> [[VECINS4]], ptr [[Q]], align 16
1026+
; CHECK-NEXT: ret void
1027+
;
1028+
entry:
1029+
%0 = load <16 x i8>, ptr %q
1030+
%vecins1 = insertelement <16 x i8> %0, i8 %s, i32 %idx1
1031+
%vecins2 = insertelement <16 x i8> %vecins1, i8 %s, i32 %idx2
1032+
%vecins3 = insertelement <16 x i8> %vecins2, i8 %s, i32 %idx3
1033+
%vecins4 = insertelement <16 x i8> %vecins3, i8 %s, i32 %idx4
1034+
store <16 x i8> %vecins4, ptr %q
1035+
ret void
1036+
}
1037+
1038+
define void @insert_store_vscale_nonconst2(ptr %q, i8 zeroext %s, i32 %idx1, i32 %idx2) {
1039+
; CHECK-LABEL: @insert_store_vscale_nonconst2(
1040+
; CHECK-NEXT: entry:
1041+
; CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 16 x i8>, ptr [[Q:%.*]], align 16
1042+
; CHECK-NEXT: [[VECINS1:%.*]] = insertelement <vscale x 16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX1:%.*]]
1043+
; CHECK-NEXT: [[VECINS2:%.*]] = insertelement <vscale x 16 x i8> [[VECINS1]], i8 [[S]], i32 [[IDX2:%.*]]
1044+
; CHECK-NEXT: store <vscale x 16 x i8> [[VECINS2]], ptr [[Q]], align 16
1045+
; CHECK-NEXT: ret void
1046+
;
1047+
entry:
1048+
%0 = load <vscale x 16 x i8>, ptr %q
1049+
%vecins1 = insertelement <vscale x 16 x i8> %0, i8 %s, i32 %idx1
1050+
%vecins2 = insertelement <vscale x 16 x i8> %vecins1, i8 %s, i32 %idx2
1051+
store <vscale x 16 x i8> %vecins2, ptr %q
1052+
ret void
1053+
}
1054+
1055+
define void @insert_store_nonconst_large_alignment2(ptr %q, i32 zeroext %s, i32 %idx1, i32 %idx2) {
1056+
; CHECK-LABEL: @insert_store_nonconst_large_alignment2(
1057+
; CHECK-NEXT: entry:
1058+
; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[IDX1:%.*]], 4
1059+
; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i32 [[IDX2:%.*]], 4
1060+
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP1]])
1061+
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP2]])
1062+
; CHECK-NEXT: [[I:%.*]] = load <4 x i32>, ptr [[Q:%.*]], align 128
1063+
; CHECK-NEXT: [[VECINS1:%.*]] = insertelement <4 x i32> [[I]], i32 [[S:%.*]], i32 [[IDX1]]
1064+
; CHECK-NEXT: [[VECINS2:%.*]] = insertelement <4 x i32> [[VECINS1]], i32 [[S]], i32 [[IDX2]]
1065+
; CHECK-NEXT: store <4 x i32> [[VECINS2]], ptr [[Q]], align 128
1066+
; CHECK-NEXT: ret void
1067+
;
1068+
entry:
1069+
%cmp1 = icmp ult i32 %idx1, 4
1070+
%cmp2 = icmp ult i32 %idx2, 4
1071+
call void @llvm.assume(i1 %cmp1)
1072+
call void @llvm.assume(i1 %cmp2)
1073+
%i = load <4 x i32>, ptr %q, align 128
1074+
%vecins1 = insertelement <4 x i32> %i, i32 %s, i32 %idx1
1075+
%vecins2 = insertelement <4 x i32> %vecins1, i32 %s, i32 %idx2
1076+
store <4 x i32> %vecins2, ptr %q, align 128
1077+
ret void
1078+
}
1079+
1080+
define void @insert_store_nonconst_align_maximum_8_2(ptr %q, i64 %s, i32 %idx1, i32 %idx2) {
1081+
; CHECK-LABEL: @insert_store_nonconst_align_maximum_8_2(
1082+
; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[IDX1:%.*]], 2
1083+
; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i32 [[IDX2:%.*]], 2
1084+
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP1]])
1085+
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP2]])
1086+
; CHECK-NEXT: [[I:%.*]] = load <8 x i64>, ptr [[Q:%.*]], align 8
1087+
; CHECK-NEXT: [[VECINS1:%.*]] = insertelement <8 x i64> [[I]], i64 [[S:%.*]], i32 [[IDX1]]
1088+
; CHECK-NEXT: [[VECINS2:%.*]] = insertelement <8 x i64> [[VECINS1]], i64 [[S]], i32 [[IDX2]]
1089+
; CHECK-NEXT: store <8 x i64> [[VECINS2]], ptr [[Q]], align 8
1090+
; CHECK-NEXT: ret void
1091+
;
1092+
%cmp1 = icmp ult i32 %idx1, 2
1093+
%cmp2 = icmp ult i32 %idx2, 2
1094+
call void @llvm.assume(i1 %cmp1)
1095+
call void @llvm.assume(i1 %cmp2)
1096+
%i = load <8 x i64>, ptr %q, align 8
1097+
%vecins1 = insertelement <8 x i64> %i, i64 %s, i32 %idx1
1098+
%vecins2 = insertelement <8 x i64> %vecins1, i64 %s, i32 %idx2
1099+
store <8 x i64> %vecins2, ptr %q, align 8
1100+
ret void
1101+
}
1102+
1103+
define void @insert_store_nonconst_align_maximum_4_2(ptr %q, i64 %s, i32 %idx1, i32 %idx2) {
1104+
; CHECK-LABEL: @insert_store_nonconst_align_maximum_4_2(
1105+
; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[IDX1:%.*]], 2
1106+
; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i32 [[IDX2:%.*]], 2
1107+
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP1]])
1108+
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP2]])
1109+
; CHECK-NEXT: [[I:%.*]] = load <8 x i64>, ptr [[Q:%.*]], align 4
1110+
; CHECK-NEXT: [[VECINS1:%.*]] = insertelement <8 x i64> [[I]], i64 [[S:%.*]], i32 [[IDX1]]
1111+
; CHECK-NEXT: [[VECINS2:%.*]] = insertelement <8 x i64> [[VECINS1]], i64 [[S]], i32 [[IDX2]]
1112+
; CHECK-NEXT: store <8 x i64> [[VECINS2]], ptr [[Q]], align 4
1113+
; CHECK-NEXT: ret void
1114+
;
1115+
%cmp1 = icmp ult i32 %idx1, 2
1116+
%cmp2 = icmp ult i32 %idx2, 2
1117+
call void @llvm.assume(i1 %cmp1)
1118+
call void @llvm.assume(i1 %cmp2)
1119+
%i = load <8 x i64>, ptr %q, align 4
1120+
%vecins1 = insertelement <8 x i64> %i, i64 %s, i32 %idx1
1121+
%vecins2 = insertelement <8 x i64> %vecins1, i64 %s, i32 %idx2
1122+
store <8 x i64> %vecins2, ptr %q, align 4
1123+
ret void
1124+
}
1125+
1126+
define void @insert_store_nonconst_align_larger_2(ptr %q, i64 %s, i32 %idx1, i32 %idx2) {
1127+
; CHECK-LABEL: @insert_store_nonconst_align_larger_2(
1128+
; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[IDX1:%.*]], 2
1129+
; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i32 [[IDX2:%.*]], 2
1130+
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP1]])
1131+
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP2]])
1132+
; CHECK-NEXT: [[I:%.*]] = load <8 x i64>, ptr [[Q:%.*]], align 4
1133+
; CHECK-NEXT: [[VECINS1:%.*]] = insertelement <8 x i64> [[I]], i64 [[S:%.*]], i32 [[IDX1]]
1134+
; CHECK-NEXT: [[VECINS2:%.*]] = insertelement <8 x i64> [[VECINS1]], i64 [[S]], i32 [[IDX2]]
1135+
; CHECK-NEXT: store <8 x i64> [[VECINS2]], ptr [[Q]], align 2
1136+
; CHECK-NEXT: ret void
1137+
;
1138+
%cmp1 = icmp ult i32 %idx1, 2
1139+
%cmp2 = icmp ult i32 %idx2, 2
1140+
call void @llvm.assume(i1 %cmp1)
1141+
call void @llvm.assume(i1 %cmp2)
1142+
%i = load <8 x i64>, ptr %q, align 4
1143+
%vecins1 = insertelement <8 x i64> %i, i64 %s, i32 %idx1
1144+
%vecins2 = insertelement <8 x i64> %vecins1, i64 %s, i32 %idx2
1145+
store <8 x i64> %vecins2, ptr %q, align 2
1146+
ret void
1147+
}

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