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maryammomaryammo
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Update the test and fix the mask type
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+37
-36
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2 files changed

+37
-36
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‎llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -206,6 +206,7 @@ let Predicates = [IsISAFuture] in {
206206
def DMSETDMRZ : XForm_AT3<31, 2, 177, (outs dmr:$AT), (ins),
207207
"dmsetdmrz $AT", NoItinerary,
208208
[(set v1024i1:$AT, (int_ppc_mma_dmsetdmrz))]>;
209+
}
209210

210211
// MMA+ accumulating/non-accumulating instructions.
211212

@@ -255,7 +256,7 @@ let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
255256

256257
def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
257258
Msk8Imm:$XMSK, Msk4Imm:$YMSK,
258-
Msk2Imm:$PMSK)),
259+
Msk4Imm:$PMSK)),
259260
(PMDMXVI8GERX4SPP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
260-
Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
261+
Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
261262
}

‎llvm/test/CodeGen/PowerPC/dmf-outer-product.ll‎

Lines changed: 34 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -37,10 +37,10 @@ define void @test_dmxvi8gerx4(ptr %vpp, ptr %vcp, ptr %resp) {
3737
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
3838
; CHECK-BE-NEXT: blr
3939
entry:
40-
%0 = load <256 x i1>, ptr %vpp, align 32
41-
%1 = load <16 x i8>, ptr %vcp, align 32
42-
%2 = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4(<256 x i1> %0, <16 x i8> %1)
43-
store <1024 x i1> %2, ptr %resp, align 64
40+
%v1 = load <256 x i1>, ptr %vpp, align 32
41+
%v2 = load <16 x i8>, ptr %vcp, align 32
42+
%call = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4(<256 x i1> %v1, <16 x i8> %v2)
43+
store <1024 x i1> %call, ptr %resp, align 64
4444
ret void
4545
}
4646

@@ -87,11 +87,11 @@ define void @test_dmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
8787
; CHECK-BE-NEXT: stxvp vsp34, 0(r6)
8888
; CHECK-BE-NEXT: blr
8989
entry:
90-
%0 = load <1024 x i1>, ptr %vop, align 64
91-
%1 = load <256 x i1>, ptr %vpp, align 32
92-
%2 = load <16 x i8>, ptr %vcp, align 32
93-
%3 = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4pp(<1024 x i1> %0, <256 x i1> %1, <16 x i8> %2)
94-
store <1024 x i1> %3, ptr %resp, align 64
90+
%v.dmr = load <1024 x i1>, ptr %vop, align 64
91+
%v1 = load <256 x i1>, ptr %vpp, align 32
92+
%v2 = load <16 x i8>, ptr %vcp, align 32
93+
%call = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4pp(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2)
94+
store <1024 x i1> %call, ptr %resp, align 64
9595
ret void
9696
}
9797

@@ -138,11 +138,11 @@ define void @test_dmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
138138
; CHECK-BE-NEXT: stxvp vsp34, 0(r6)
139139
; CHECK-BE-NEXT: blr
140140
entry:
141-
%0 = load <1024 x i1>, ptr %vop, align 64
142-
%1 = load <256 x i1>, ptr %vpp, align 32
143-
%2 = load <16 x i8>, ptr %vcp, align 32
144-
%3 = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4spp(<1024 x i1> %0, <256 x i1> %1, <16 x i8> %2)
145-
store <1024 x i1> %3, ptr %resp, align 64
141+
%v.dmr = load <1024 x i1>, ptr %vop, align 64
142+
%v1 = load <256 x i1>, ptr %vpp, align 32
143+
%v2 = load <16 x i8>, ptr %vcp, align 32
144+
%call = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4spp(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2)
145+
store <1024 x i1> %call, ptr %resp, align 64
146146
ret void
147147
}
148148

@@ -160,7 +160,7 @@ define void @test_pmdmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
160160
; CHECK-NEXT: lxv v3, 0(r4)
161161
; CHECK-NEXT: lxv vs0, 0(r5)
162162
; CHECK-NEXT: lxv v2, 16(r4)
163-
; CHECK-NEXT: pmdmxvi8gerx4pp dmr0, vsp34, vs0, 0, 0, 0
163+
; CHECK-NEXT: pmdmxvi8gerx4pp dmr0, vsp34, vs0, 42, 7, 9
164164
; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
165165
; CHECK-NEXT: stxvp vsp34, 96(r6)
166166
; CHECK-NEXT: stxvp vsp36, 64(r6)
@@ -180,7 +180,7 @@ define void @test_pmdmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
180180
; CHECK-BE-NEXT: lxv v3, 16(r4)
181181
; CHECK-BE-NEXT: lxv vs0, 0(r5)
182182
; CHECK-BE-NEXT: lxv v2, 0(r4)
183-
; CHECK-BE-NEXT: pmdmxvi8gerx4pp dmr0, vsp34, vs0, 0, 0, 0
183+
; CHECK-BE-NEXT: pmdmxvi8gerx4pp dmr0, vsp34, vs0, 42, 7, 9
184184
; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
185185
; CHECK-BE-NEXT: stxvp vsp36, 96(r6)
186186
; CHECK-BE-NEXT: stxvp vsp34, 64(r6)
@@ -189,11 +189,11 @@ define void @test_pmdmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
189189
; CHECK-BE-NEXT: stxvp vsp34, 0(r6)
190190
; CHECK-BE-NEXT: blr
191191
entry:
192-
%0 = load <1024 x i1>, ptr %vop, align 64
193-
%1 = load <256 x i1>, ptr %vpp, align 32
194-
%2 = load <16 x i8>, ptr %vcp, align 32
195-
%3 = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4pp(<1024 x i1> %0, <256 x i1> %1, <16 x i8> %2, i32 0, i32 0, i32 0)
196-
store <1024 x i1> %3, ptr %resp, align 64
192+
%v.dmr = load <1024 x i1>, ptr %vop, align 64
193+
%v1 = load <256 x i1>, ptr %vpp, align 32
194+
%v2 = load <16 x i8>, ptr %vcp, align 32
195+
%call = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4pp(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2, i32 42, i32 7, i32 9)
196+
store <1024 x i1> %call, ptr %resp, align 64
197197
ret void
198198
}
199199

@@ -205,7 +205,7 @@ define void @test_pmdmxvi8gerx4(ptr %vpp, ptr %vcp, ptr %resp) {
205205
; CHECK-NEXT: lxv v3, 0(r3)
206206
; CHECK-NEXT: lxv vs0, 0(r4)
207207
; CHECK-NEXT: lxv v2, 16(r3)
208-
; CHECK-NEXT: pmdmxvi8gerx4 dmr0, vsp34, vs0, 0, 0, 0
208+
; CHECK-NEXT: pmdmxvi8gerx4 dmr0, vsp34, vs0, 55, 5, 10
209209
; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
210210
; CHECK-NEXT: stxvp vsp34, 96(r5)
211211
; CHECK-NEXT: stxvp vsp36, 64(r5)
@@ -219,7 +219,7 @@ define void @test_pmdmxvi8gerx4(ptr %vpp, ptr %vcp, ptr %resp) {
219219
; CHECK-BE-NEXT: lxv v3, 16(r3)
220220
; CHECK-BE-NEXT: lxv vs0, 0(r4)
221221
; CHECK-BE-NEXT: lxv v2, 0(r3)
222-
; CHECK-BE-NEXT: pmdmxvi8gerx4 dmr0, vsp34, vs0, 0, 0, 0
222+
; CHECK-BE-NEXT: pmdmxvi8gerx4 dmr0, vsp34, vs0, 55, 5, 10
223223
; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
224224
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
225225
; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
@@ -228,10 +228,10 @@ define void @test_pmdmxvi8gerx4(ptr %vpp, ptr %vcp, ptr %resp) {
228228
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
229229
; CHECK-BE-NEXT: blr
230230
entry:
231-
%0 = load <256 x i1>, ptr %vpp, align 32
232-
%1 = load <16 x i8>, ptr %vcp, align 32
233-
%2 = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4(<256 x i1> %0, <16 x i8> %1, i32 0, i32 0, i32 0)
234-
store <1024 x i1> %2, ptr %resp, align 64
231+
%v1 = load <256 x i1>, ptr %vpp, align 32
232+
%v2 = load <16 x i8>, ptr %vcp, align 32
233+
%call = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4(<256 x i1> %v1, <16 x i8> %v2, i32 55, i32 5, i32 10)
234+
store <1024 x i1> %call, ptr %resp, align 64
235235
ret void
236236
}
237237

@@ -249,7 +249,7 @@ define dso_local void @test_pmdmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %
249249
; CHECK-NEXT: lxv v3, 0(r4)
250250
; CHECK-NEXT: lxv vs0, 0(r5)
251251
; CHECK-NEXT: lxv v2, 16(r4)
252-
; CHECK-NEXT: pmdmxvi8gerx4spp dmr0, vsp34, vs0, 0, 0, 0
252+
; CHECK-NEXT: pmdmxvi8gerx4spp dmr0, vsp34, vs0, 100, 6, 12
253253
; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
254254
; CHECK-NEXT: stxvp vsp34, 96(r6)
255255
; CHECK-NEXT: stxvp vsp36, 64(r6)
@@ -269,7 +269,7 @@ define dso_local void @test_pmdmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %
269269
; CHECK-BE-NEXT: lxv v3, 16(r4)
270270
; CHECK-BE-NEXT: lxv vs0, 0(r5)
271271
; CHECK-BE-NEXT: lxv v2, 0(r4)
272-
; CHECK-BE-NEXT: pmdmxvi8gerx4spp dmr0, vsp34, vs0, 0, 0, 0
272+
; CHECK-BE-NEXT: pmdmxvi8gerx4spp dmr0, vsp34, vs0, 100, 6, 12
273273
; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
274274
; CHECK-BE-NEXT: stxvp vsp36, 96(r6)
275275
; CHECK-BE-NEXT: stxvp vsp34, 64(r6)
@@ -278,10 +278,10 @@ define dso_local void @test_pmdmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %
278278
; CHECK-BE-NEXT: stxvp vsp34, 0(r6)
279279
; CHECK-BE-NEXT: blr
280280
entry:
281-
%0 = load <1024 x i1>, ptr %vop, align 64
282-
%1 = load <256 x i1>, ptr %vpp, align 32
283-
%2 = load <16 x i8>, ptr %vcp, align 32
284-
%3 = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4spp(<1024 x i1> %0, <256 x i1> %1, <16 x i8> %2, i32 0, i32 0, i32 0)
285-
store <1024 x i1> %3, ptr %resp, align 64
281+
%v.dmr = load <1024 x i1>, ptr %vop, align 64
282+
%v1 = load <256 x i1>, ptr %vpp, align 32
283+
%v2 = load <16 x i8>, ptr %vcp, align 32
284+
%call = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4spp(<1024 x i1> %v.dmr, <256 x i1> %v1, <16 x i8> %v2, i32 100, i32 6, i32 12)
285+
store <1024 x i1> %call, ptr %resp, align 64
286286
ret void
287287
}

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