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[Test] Pre-submit tests for #101294
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32 %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64 %s
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define i32 @add_shl_oneUse(i32 %x, i32 %y) nounwind {
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; RV32-LABEL: add_shl_oneUse:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a0, a0, 3
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: addi a0, a0, 984
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; RV32-NEXT: ret
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;
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; RV64-LABEL: add_shl_oneUse:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a0, a0, 3
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: addiw a0, a0, 984
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; RV64-NEXT: ret
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%add.0 = add i32 %x, 123
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%shl = shl i32 %add.0, 3
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%add.1 = add i32 %shl, %y
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ret i32 %add.1
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}
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define void @add_shl_addmoreOneUse_in_store(ptr %array1, i32 %a, i32 %b) {
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; RV32-LABEL: add_shl_addmoreOneUse_in_store:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: addi a3, a1, 5
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; RV32-NEXT: slli a4, a3, 2
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; RV32-NEXT: add a4, a0, a4
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; RV32-NEXT: sw a2, 0(a4)
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; RV32-NEXT: slli a1, a1, 2
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: sw a2, 24(a0)
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; RV32-NEXT: sw a3, 140(a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: add_shl_addmoreOneUse_in_store:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: addiw a3, a1, 5
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; RV64-NEXT: slli a4, a3, 2
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; RV64-NEXT: add a4, a0, a4
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; RV64-NEXT: sw a2, 0(a4)
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; RV64-NEXT: sext.w a1, a1
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; RV64-NEXT: slli a1, a1, 2
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: sw a2, 24(a0)
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; RV64-NEXT: sw a3, 140(a0)
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; RV64-NEXT: ret
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entry:
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%add = add nsw i32 %a, 5
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%arrayidx = getelementptr inbounds i32, ptr %array1, i32 %add
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store i32 %b, ptr %arrayidx
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%0 = getelementptr i32, ptr %array1, i32 %a
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%arrayidx3 = getelementptr i8, ptr %0, i32 24
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store i32 %b, ptr %arrayidx3
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%arrayidx5 = getelementptr i8, ptr %0, i32 140
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store i32 %add, ptr %arrayidx5
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ret void
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}

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