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[RISCV,GISel] Add legalizer for G_ABS (#67577)
Lower G_ABS to support llvm.abs.* intrinsics.
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‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

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@@ -167,6 +167,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
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.widenScalarToNextPow2(0);
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}
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getActionDefinitionsBuilder(G_ABS).lower();
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getLegacyLegalizerInfo().computeTables();
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}
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‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-abs.mir‎

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: abs_i8
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: abs_i8
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ASSERT_ZEXT]], [[C1]](s32)
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
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; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASSERT_ZEXT]], [[ASHR1]]
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; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR1]]
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C2]]
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; CHECK-NEXT: $x10 = COPY [[AND]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%1:_(s32) = COPY $x10
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%2:_(s32) = G_ASSERT_ZEXT %1, 8
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%0:_(s8) = G_TRUNC %2(s32)
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%3:_(s8) = G_ABS %0
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%4:_(s32) = G_ZEXT %3(s8)
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$x10 = COPY %4(s32)
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PseudoRET implicit $x10
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...
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---
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name: abs_i16
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: abs_i16
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ASSERT_SEXT]], [[C1]](s32)
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
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; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASSERT_SEXT]], [[ASHR1]]
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; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR1]]
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[XOR]], [[C2]](s32)
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; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C2]](s32)
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; CHECK-NEXT: $x10 = COPY [[ASHR2]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%1:_(s32) = COPY $x10
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%2:_(s32) = G_ASSERT_SEXT %1, 16
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%0:_(s16) = G_TRUNC %2(s32)
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%3:_(s16) = G_ABS %0
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%4:_(s32) = G_SEXT %3(s16)
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$x10 = COPY %4(s32)
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PseudoRET implicit $x10
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...
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---
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name: abs_i32
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: abs_i32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ASHR]]
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; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR]]
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; CHECK-NEXT: $x10 = COPY [[XOR]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $x10
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%1:_(s32) = G_ABS %0
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$x10 = COPY %1(s32)
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PseudoRET implicit $x10
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...
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---
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name: abs_i64
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: abs_i64
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C1]](s32)
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ASHR]]
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[ASHR]]
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; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[ASHR1]]
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
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; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
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; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR]]
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; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[ADD2]], [[ASHR1]]
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; CHECK-NEXT: $x10 = COPY [[XOR]](s32)
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; CHECK-NEXT: $x11 = COPY [[XOR1]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
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%1:_(s32) = COPY $x10
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%2:_(s32) = COPY $x11
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%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
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%3:_(s64) = G_ABS %0
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%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
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$x10 = COPY %4(s32)
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$x11 = COPY %5(s32)
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PseudoRET implicit $x10, implicit $x11
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...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-abs.mir‎

Lines changed: 105 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,105 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: abs_i8
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: abs_i8
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 8
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_ZEXT]](s64)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C1]](s32)
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
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; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
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; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_ZEXT]](s64)
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC1]], [[ASHR1]]
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
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; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR1]](s32)
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; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ANYEXT]], [[ANYEXT1]]
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C2]]
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; CHECK-NEXT: $x10 = COPY [[AND]](s64)
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; CHECK-NEXT: PseudoRET implicit $x10
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%1:_(s64) = COPY $x10
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%2:_(s64) = G_ASSERT_ZEXT %1, 8
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%0:_(s8) = G_TRUNC %2(s64)
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%3:_(s8) = G_ABS %0
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%4:_(s64) = G_ZEXT %3(s8)
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$x10 = COPY %4(s64)
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PseudoRET implicit $x10
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...
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---
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name: abs_i16
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: abs_i16
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 16
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_SEXT]](s64)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C1]](s32)
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
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; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
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; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_SEXT]](s64)
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC1]], [[ASHR1]]
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
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; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR1]](s32)
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; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ANYEXT]], [[ANYEXT1]]
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
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; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[XOR]], [[C2]](s64)
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; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C2]](s64)
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; CHECK-NEXT: $x10 = COPY [[ASHR2]](s64)
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; CHECK-NEXT: PseudoRET implicit $x10
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%1:_(s64) = COPY $x10
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%2:_(s64) = G_ASSERT_SEXT %1, 16
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%0:_(s16) = G_TRUNC %2(s64)
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%3:_(s16) = G_ABS %0
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%4:_(s64) = G_SEXT %3(s16)
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$x10 = COPY %4(s64)
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PseudoRET implicit $x10
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...
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---
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name: abs_i32
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: abs_i32
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_SEXT]](s64)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[TRUNC]], [[C]](s32)
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[ASHR]]
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
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; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR]](s32)
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; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ANYEXT]], [[ANYEXT1]]
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; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[XOR]], 32
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; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
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; CHECK-NEXT: PseudoRET implicit $x10
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%1:_(s64) = COPY $x10
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%2:_(s64) = G_ASSERT_SEXT %1, 32
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%0:_(s32) = G_TRUNC %2(s64)
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%3:_(s32) = G_ABS %0
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%4:_(s64) = G_SEXT %3(s32)
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$x10 = COPY %4(s64)
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PseudoRET implicit $x10
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...
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---
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name: abs_i64
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: abs_i64
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64)
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ASHR]]
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; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR]]
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; CHECK-NEXT: $x10 = COPY [[XOR]](s64)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(s64) = COPY $x10
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%1:_(s64) = G_ABS %0
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$x10 = COPY %1(s64)
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PseudoRET implicit $x10
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...

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