Update according to comments

Signed-off-by: Alan Li <[email protected]>

Author: lialan

llvm/lib/Target/AMDGPU/AMDGPU.td

@@ -2520,6 +2520,8 @@ def HasXF32Insts : Predicate<"Subtarget->hasXF32Insts()">,
 def HasAshrPkInsts : Predicate<"Subtarget->hasAshrPkInsts()">,
   AssemblerPredicate<(all_of FeatureAshrPkInsts)>;
 
+def HasLShlAddB64 : Predicate<"Subtarget->hasLshlAddB64()">;
+
 // Include AMDGPU TD files
 include "SISchedule.td"
 include "GCNProcessors.td"

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

@@ -26,6 +26,7 @@
 #include "llvm/ADT/ScopeExit.h"
 #include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
+#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/GlobalISel/Utils.h"
@@ -743,22 +744,16 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
           .minScalar(0, S16)
           .widenScalarToNextMultipleOf(0, 32)
           .maxScalar(0, S32);
-      if (ST.hasLshlAddB64())
-        getActionDefinitionsBuilder(G_ADD)
-            .legalFor({S64, S32, S16, V2S16})
-            .clampMaxNumElementsStrict(0, S16, 2)
-            .scalarize(0)
-            .minScalar(0, S16)
-            .widenScalarToNextMultipleOf(0, 32)
-            .maxScalar(0, S32);
-      else
-        getActionDefinitionsBuilder(G_ADD)
-            .legalFor({S32, S16, V2S16})
-            .clampMaxNumElementsStrict(0, S16, 2)
-            .scalarize(0)
-            .minScalar(0, S16)
-            .widenScalarToNextMultipleOf(0, 32)
-            .maxScalar(0, S32);
+
+      getActionDefinitionsBuilder(G_ADD)
+          .legalFor(ST.hasLshlAddB64()
+                        ? std::initializer_list<LLT>{S32, S16, V2S16, S64}
+                        : std::initializer_list<LLT>{S32, S16, V2S16})
+          .clampMaxNumElementsStrict(0, S16, 2)
+          .scalarize(0)
+          .minScalar(0, S16)
+          .widenScalarToNextMultipleOf(0, 32)
+          .maxScalar(0, S32);
     }
 
     if (ST.hasScalarSMulU64()) {

llvm/lib/Target/AMDGPU/VOP3Instructions.td

@@ -762,7 +762,7 @@ def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32_e64>;
 def : ThreeOp_i32_Pats<or, or, V_OR3_B32_e64>;
 def : ThreeOp_i32_Pats<xor, add, V_XAD_U32_e64>;
 
-let SubtargetPredicate = isGFX940Plus in {
+let SubtargetPredicate = HasLShlAddB64 in {
 // TODO: Canonicalize these in the target specific CombinerHelper?
 def : GCNPat<
   (ptradd (shl i64:$src0, i32:$shift), i64:$src1),
@@ -778,17 +778,16 @@ def : GCNPat<
   (ptradd i64:$src0, i64:$src1),
   (V_LSHL_ADD_U64_e64 VSrc_b64:$src0, (i32 0), VSrc_b64:$src1)
 >;
-}
 
-def : GCNPat<
- (DivergentBinFrag<mul> i32:$src0, IsPow2Plus1:$src1),
- (V_LSHL_ADD_U32_e64 i32:$src0, (i32 (Log2_32 imm:$src1)), i32:$src0)>;
-
-let SubtargetPredicate = isGFX940Plus in
 def : GCNPat<
   (ThreeOpFrag<shl_0_to_4, add> i64:$src0, i32:$src1, i64:$src2),
   (V_LSHL_ADD_U64_e64 VSrc_b64:$src0, VSrc_b32:$src1, VSrc_b64:$src2)
 >;
+} // End SubtargetPredicate = HasLShlAddB64
+
+def : GCNPat<
+ (DivergentBinFrag<mul> i32:$src0, IsPow2Plus1:$src1),
+ (V_LSHL_ADD_U32_e64 i32:$src0, (i32 (Log2_32 imm:$src1)), i32:$src0)>;
 
 def : VOPBinOpClampPat<saddsat, V_ADD_I32_e64, i32>;
 def : VOPBinOpClampPat<ssubsat, V_SUB_I32_e64, i32>;